feat(zynqmp): resolve the misra 10.1 warnings

MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The operand to the operator does not have an essentially unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I97bbc056f4fee167742429e144144ba793bf77b3

diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index bf262c42fb8863c3446a30beddfcaccc82735848..a0900c444c4d516cf383d27b3c6eac2c3e9d7a23 100644 (file)
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -24,36 +24,36 @@
  * CPU#                        5:6             00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3
  */
 
-#define FSBL_FLAGS_ESTATE_SHIFT                0
-#define FSBL_FLAGS_ESTATE_MASK         (1 << FSBL_FLAGS_ESTATE_SHIFT)
-#define FSBL_FLAGS_ESTATE_A64          0
-#define FSBL_FLAGS_ESTATE_A32          1
-
-#define FSBL_FLAGS_ENDIAN_SHIFT                1
-#define FSBL_FLAGS_ENDIAN_MASK         (1 << FSBL_FLAGS_ENDIAN_SHIFT)
-#define FSBL_FLAGS_ENDIAN_LE           0
-#define FSBL_FLAGS_ENDIAN_BE           1
-
-#define FSBL_FLAGS_TZ_SHIFT            2
-#define FSBL_FLAGS_TZ_MASK             (1 << FSBL_FLAGS_TZ_SHIFT)
-#define FSBL_FLAGS_NON_SECURE          0
-#define FSBL_FLAGS_SECURE              1
-
-#define FSBL_FLAGS_EL_SHIFT            3
-#define FSBL_FLAGS_EL_MASK             (3 << FSBL_FLAGS_EL_SHIFT)
-#define FSBL_FLAGS_EL0                 0
-#define FSBL_FLAGS_EL1                 1
-#define FSBL_FLAGS_EL2                 2
-#define FSBL_FLAGS_EL3                 3
-
-#define FSBL_FLAGS_CPU_SHIFT           5
-#define FSBL_FLAGS_CPU_MASK            (3 << FSBL_FLAGS_CPU_SHIFT)
-#define FSBL_FLAGS_A53_0               0
-#define FSBL_FLAGS_A53_1               1
-#define FSBL_FLAGS_A53_2               2
-#define FSBL_FLAGS_A53_3               3
-
-#define FSBL_MAX_PARTITIONS            8
+#define FSBL_FLAGS_ESTATE_SHIFT                0U
+#define FSBL_FLAGS_ESTATE_MASK         (1U << FSBL_FLAGS_ESTATE_SHIFT)
+#define FSBL_FLAGS_ESTATE_A64          0U
+#define FSBL_FLAGS_ESTATE_A32          1U
+
+#define FSBL_FLAGS_ENDIAN_SHIFT                1U
+#define FSBL_FLAGS_ENDIAN_MASK         (1U << FSBL_FLAGS_ENDIAN_SHIFT)
+#define FSBL_FLAGS_ENDIAN_LE           0U
+#define FSBL_FLAGS_ENDIAN_BE           1U
+
+#define FSBL_FLAGS_TZ_SHIFT            2U
+#define FSBL_FLAGS_TZ_MASK             (1U << FSBL_FLAGS_TZ_SHIFT)
+#define FSBL_FLAGS_NON_SECURE          0U
+#define FSBL_FLAGS_SECURE              1U
+
+#define FSBL_FLAGS_EL_SHIFT            3U
+#define FSBL_FLAGS_EL_MASK             (3U << FSBL_FLAGS_EL_SHIFT)
+#define FSBL_FLAGS_EL0                 0U
+#define FSBL_FLAGS_EL1                 1U
+#define FSBL_FLAGS_EL2                 2U
+#define FSBL_FLAGS_EL3                 3U
+
+#define FSBL_FLAGS_CPU_SHIFT           5U
+#define FSBL_FLAGS_CPU_MASK            (3U << FSBL_FLAGS_CPU_SHIFT)
+#define FSBL_FLAGS_A53_0               0U
+#define FSBL_FLAGS_A53_1               1U
+#define FSBL_FLAGS_A53_2               2U
+#define FSBL_FLAGS_A53_3               3U
+
+#define FSBL_MAX_PARTITIONS            8U
 
 /* Structure corresponding to each partition entry */
 struct xfsbl_partition {
@@ -193,8 +193,8 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
         */
        for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) {
                entry_point_info_t *image;
-               int32_t target_estate, target_secure;
-               int32_t target_cpu, target_endianness, target_el;
+               int32_t target_estate, target_secure, target_cpu;
+               uint32_t target_endianness, target_el;
 
                VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i,
                        ATFHandoffParams->partition[i].entry_point,

diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 5890311f7066bdc242e15c924040641b7d2bcacb..3946e9b629075327490e291ba4a79287c1282b66 100644 (file)
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -215,8 +215,8 @@ static const struct {
 #define ZYNQMP_PL_STATUS_MASK  BIT(ZYNQMP_PL_STATUS_BIT)
 #define ZYNQMP_CSU_VERSION_MASK        ~(ZYNQMP_PL_STATUS_MASK)
 
-#define SILICON_ID_XCK24       0x4714093
-#define SILICON_ID_XCK26       0x4724093
+#define SILICON_ID_XCK24       0x4714093U
+#define SILICON_ID_XCK26       0x4724093U
 
 static char *zynqmp_get_silicon_idcode_name(void)
 {
@@ -317,7 +317,7 @@ static uint32_t zynqmp_get_ps_ver(void)
        ver &= ZYNQMP_PS_VER_MASK;
        ver >>= ZYNQMP_PS_VER_SHIFT;
 
-       return ver + 1;
+       return ver + 1U;
 }
 
 static void zynqmp_print_platform_name(void)

diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index 19b6937cbf69f0049da31471b073563f21cc9193..877127bbc42ee0d49f50f611b48c9ac27d82a75c 100644 (file)
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -163,40 +163,40 @@
 #define ZYNQMP_CSU_VERSION_SILICON     0
 #define ZYNQMP_CSU_VERSION_QEMU                3
 
-#define ZYNQMP_RTL_VER_MASK            0xFF0
+#define ZYNQMP_RTL_VER_MASK            0xFF0U
 #define ZYNQMP_RTL_VER_SHIFT           4
 
-#define ZYNQMP_PS_VER_MASK             0xF
+#define ZYNQMP_PS_VER_MASK             0xFU
 #define ZYNQMP_PS_VER_SHIFT            0
 
 #define ZYNQMP_CSU_BASEADDR            U(0xFFCA0000)
-#define ZYNQMP_CSU_IDCODE_OFFSET       0x40
+#define ZYNQMP_CSU_IDCODE_OFFSET       0x40U
 
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT      0
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK       (0xFFF << \
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT      0U
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK       (0xFFFU << \
                                        ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
 #define ZYNQMP_CSU_IDCODE_XILINX_ID            0x093
 
-#define ZYNQMP_CSU_IDCODE_SVD_SHIFT            12
-#define ZYNQMP_CSU_IDCODE_SVD_MASK             (0x7 << \
+#define ZYNQMP_CSU_IDCODE_SVD_SHIFT            12U
+#define ZYNQMP_CSU_IDCODE_SVD_MASK             (0x7U << \
                                                 ZYNQMP_CSU_IDCODE_SVD_SHIFT)
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT    15
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK     (0xF << \
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT    15U
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK     (0xFU << \
                                        ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT     19
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK      (0x3 << \
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT     19U
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK      (0x3U << \
                                        ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
-#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT         21
-#define ZYNQMP_CSU_IDCODE_FAMILY_MASK          (0x7F << \
+#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT         21U
+#define ZYNQMP_CSU_IDCODE_FAMILY_MASK          (0x7FU << \
                                        ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
 #define ZYNQMP_CSU_IDCODE_FAMILY               0x23
 
-#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT       28
-#define ZYNQMP_CSU_IDCODE_REVISION_MASK                (0xF << \
+#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT       28U
+#define ZYNQMP_CSU_IDCODE_REVISION_MASK                (0xFU << \
                                        ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
-#define ZYNQMP_CSU_IDCODE_REVISION             0
+#define ZYNQMP_CSU_IDCODE_REVISION             0U
 
-#define ZYNQMP_CSU_VERSION_OFFSET      0x44
+#define ZYNQMP_CSU_VERSION_OFFSET      0x44U
 
 /* Efuse */
 #define EFUSE_BASEADDR         U(0xFFCC0000)

diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 655a7765cfd2573a620f1faa54d53bb3c868b60d..b7408b1dae7e7142dc0b08622bc7dcf9563bdbcc 100644 (file)
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -176,7 +176,7 @@ static int32_t zynqmp_validate_power_state(uint32_t power_state,
 {
        VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
 
-       int32_t pstate = psci_get_pstate_type(power_state);
+       uint32_t pstate = psci_get_pstate_type(power_state);
 
        assert(req_state);
 

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index bfc6e44e4e258f97543973b0d54f3c82be4c7bf0..c6bed7d5deedbf243c0618f60aae0d8c1e9eefd0 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2610,7 +2610,7 @@ enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id,
                }
        }
 
-       for (i = 0; i < 3; i++) {
+       for (i = 0; i < 3U; i++) {
                parents[i] = clk_parents[index + i];
                if (clk_parents[index + i] == CLK_NA_PARENT) {
                        break;

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 1380895c2ca12059c04a4193901ceac30b97605f..8a5a25a05d3bc20d9f9cef83d4d2262208bc3175 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -35,7 +35,7 @@ static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(uint32_t *mode)
 
        val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
        val &= ZYNQMP_SLSPLIT_MASK;
-       if (val == 0) {
+       if (val == 0U) {
                *mode = PM_RPU_MODE_LOCKSTEP;
        } else {
                *mode = PM_RPU_MODE_SPLIT;
@@ -309,7 +309,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
                return ret;
        }
 
-       if ((val & mask) == 0) {
+       if ((val & mask) == 0U) {
                ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
                if (ret != PM_RET_SUCCESS) {
                        return ret;
@@ -325,7 +325,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
                        goto reset_release;
                }
 
-               if (value == 0) {
+               if (value == 0U) {
                        ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
                                            (ZYNQMP_SD_ITAPDLYENA_MASK <<
                                             shift), 0);

diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index 8eb197a4a6d509c0cd0f7ab91b0cb4d8d3cb7ea2..d48df55173f4a91badf745f7987c63466b5dd01c 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -17,10 +17,10 @@
  * Version number is a 32bit value, like:
  * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
  */
-#define PM_VERSION_MAJOR       1
-#define PM_VERSION_MINOR       1
+#define PM_VERSION_MAJOR       1U
+#define PM_VERSION_MINOR       1U
 
-#define PM_VERSION     ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
+#define PM_VERSION     ((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR)
 
 /**
  * PM API versions

diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index 0b366d79740b0e9ecbc9f172ada2faac4e1c4964..a136ebce5de1bb27d553c8c200f1743c1d7799a9 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -214,7 +214,7 @@ int32_t pm_setup(void)
                ERROR("BL31: Platform Management API version error. Expected: "
                      "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR,
                      PM_VERSION_MINOR, pm_ctx.api_version >> 16,
-                     pm_ctx.api_version & 0xFFFF);
+                     pm_ctx.api_version & 0xFFFFU);
                return -EINVAL;
        }