#if RCAR_BL2_DCACHE == 1
NOTICE("BL2: D-Cache enable\n");
rcar_configure_mmu_el3(BL2_BASE,
- RCAR_SYSRAM_LIMIT - BL2_BASE,
+ BL2_END - BL2_BASE,
BL2_RO_BASE, BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
* size plus a little space for growth. */
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if RCAR_LSI == RCAR_E3
-#define RCAR_SYSRAM_LIMIT U(0xE6320000)
+#define BL2_LIMIT U(0xE6320000)
#else
-#define RCAR_SYSRAM_LIMIT U(0xE6360000)
+#define BL2_LIMIT U(0xE6360000)
#endif
#define BL2_BASE U(0xE6304000)
#if RCAR_LSI == RCAR_E3
-#define BL2_LIMIT U(0xE6318000)
+#define BL2_IMAGE_LIMIT U(0xE6318000)
#else
-#define BL2_LIMIT U(0xE632E800)
+#define BL2_IMAGE_LIMIT U(0xE632E800)
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
#define DEVICE_RCAR_SIZE U(0x00300000)
#define DEVICE_RCAR_BASE2 U(0xE6360000)
#define DEVICE_RCAR_SIZE2 U(0x19CA0000)
-#define DEVICE_SRAM_BASE U(0xE6310000)
+#define DEVICE_SRAM_BASE U(0xE6300000)
#define DEVICE_SRAM_SIZE U(0x00002000)
#define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
#define DEVICE_SRAM_STACK_SIZE U(0x00001000)