rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.38.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I49cf8f778b849a6ee97bc9f6948c45b07dc467b1

diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 1d6e83a2c70847174355e08ce26a6689ecbfcff2..77a07f72abf1fe7a48d24e8f94bb23d18e56d015 100644 (file)
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -2383,37 +2383,6 @@ static void dbsc_regset_post(void)
        mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
        mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
 
-#ifdef DDR_BACKUPMODE
-       if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
-#ifdef DDR_BACKUPMODE_HALF     /* for Half channel(ch0,1 only) */
-               DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
-               send_dbcmd(0x08040001);
-               wait_dbcmd();
-               send_dbcmd(0x0A040001);
-               wait_dbcmd();
-               send_dbcmd(0x04040010);
-               wait_dbcmd();
-
-               if (prr_product == PRR_PRODUCT_H3) {
-                       send_dbcmd(0x08140001);
-                       wait_dbcmd();
-                       send_dbcmd(0x0A140001);
-                       wait_dbcmd();
-                       send_dbcmd(0x04140010);
-                       wait_dbcmd();
-               }
-#else /* DDR_BACKUPMODE_HALF                              //for All channels */
-               send_dbcmd(0x08840001);
-               wait_dbcmd();
-               send_dbcmd(0x0A840001);
-               wait_dbcmd();
-
-               send_dbcmd(0x04840010);
-               wait_dbcmd();
-#endif /* DDR_BACKUPMODE_HALF */
-       }
-#endif /* DDR_BACKUPMODE */
-
 #if RCAR_REWT_TRAINING != 0
        /* Periodic-WriteDQ Training seeting */
        if (((prr_product == PRR_PRODUCT_H3) &&
@@ -2422,12 +2391,7 @@ static void dbsc_regset_post(void)
             (prr_cut == PRR_PRODUCT_10))) {
                /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
        } else {
-               /*
-                * H3 Ver.2.0 or later/M3-W Ver.1.1 or
-                * later/M3-N/V3H -> Periodic-WriteDQ Training seeting
-                */
-
-               /* Periodic WriteDQ Training seeting */
+               /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
                mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
 
                ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
@@ -2440,7 +2404,6 @@ static void dbsc_regset_post(void)
                                             _reg_PI_WDQLVL_CS_MAP));
                ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
                ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
-               ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
                ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
                ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
                ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
@@ -2458,8 +2421,10 @@ static void dbsc_regset_post(void)
                mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
        }
 #endif /* RCAR_REWT_TRAINING */
-       /* periodic dram zqcal and phy ctrl update enable */
+       /* periodic dram zqcal enable */
        mmio_write_32(DBSC_DBCALCNF, 0x01000010);
+
+       /* periodic phy ctrl update enable */
        if (((prr_product == PRR_PRODUCT_H3) &&
             (prr_cut <= PRR_PRODUCT_11)) ||
            ((prr_product == PRR_PRODUCT_M3) &&
@@ -2477,7 +2442,36 @@ static void dbsc_regset_post(void)
 #endif /* RCAR_DRAM_SPLIT == 2 */
        }
 
+#ifdef DDR_BACKUPMODE
+       /* SRX */
+       if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
+#ifdef DDR_BACKUPMODE_HALF             /* for Half channel(ch0, 1 only) */
+               NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
+               send_dbcmd(0x0A040001);
+               if (Prr_Product == PRR_PRODUCT_H3)
+                       send_dbcmd(0x0A140001);
+#else /* DDR_BACKUPMODE_HALF */                /* for All channels */
+               send_dbcmd(0x0A840001);
+#endif /* DDR_BACKUPMODE_HALF */
+       }
+#endif /* DDR_BACKUPMODE */
+
+       /* set Auto Refresh */
        mmio_write_32(DBSC_DBRFEN, 0x00000001);
+
+#if RCAR_REWT_TRAINING != 0
+       /* Periodic WriteDQ Traning */
+       if (((prr_product == PRR_PRODUCT_H3) &&
+            (prr_cut <= PRR_PRODUCT_11)) ||
+           ((prr_product == PRR_PRODUCT_M3) &&
+            (prr_cut == PRR_PRODUCT_10))) {
+               /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
+       } else {
+               /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
+               ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
+       }
+#endif /* RCAR_REWT_TRAINING */
+
        /* dram access enable */
        mmio_write_32(DBSC_DBACEN, 0x00000001);
 
@@ -3026,6 +3020,9 @@ static uint32_t init_ddr(void)
                return INITDRAM_ERR_O;
        MSG_LF(__func__ ":5\n");
 
+       /* Dummy PDE */
+       send_dbcmd(0x08840000);
+
        /* PDX */
        send_dbcmd(0x08840001);
 

diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index f8caade2734ce7559d06798d1109296a2503d79a..878f5ec43de51bb4929d38140158db79d6d4f08f 100644 (file)
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -1571,8 +1571,13 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
 {
        uint32_t md;
 
-       md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
-       md = (md | (md >> 1)) & 0x3;
+       if (prr_product == PRR_PRODUCT_V3H) {
+               md = (mmio_read_32(RST_MODEMR) >> 19) & 0x1;
+               md = (md | (md << 1)) & 0x3; /* 0 or 3 */
+       } else {
+               md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
+               md = (md | (md >> 1)) & 0x3;
+       }
        switch (md) {
        case 0x0:
                *mbps = 3200;

diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index 5047e5cc208b80fa6f2fc5876da9e00c06e7c2c4..870b357f35de887220aef3bb16440f4eedd97e4d 100644 (file)
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_DDR_VERSION       "rev.0.37"
+#define RCAR_DDR_VERSION       "rev.0.38"
 #define DRAM_CH_CNT            0x04
 #define SLICE_CNT              0x04
 #define CS_CNT                 0x02
@@ -22,7 +22,7 @@
 
 /* for ddr deisity setting */
 #define DBMEMCONF_REG(d3, row, bank, col, dw)  \
-       ((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
+       (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
 
 #define DBMEMCONF_REGD(density)                \
        (DBMEMCONF_REG((density) % 2, ((density) + 1) / \