docs(security): rename Makalu and SB optimisation

Changing Makalu reference to the public name Cortex-A715. Also, added
a note on use of SB instruction for all CPUs supporting ENABLE_FEAT_SB.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I98bd36c684fa7ae79bd4e8e641fd73404435c202

diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst
index 08bfdc458e7a254d8bd8113c09432f426cfce52f..d73e74b6bcd97cd08e9cf36e160ea0d9c2a7ee4a 100644 (file)
--- a/docs/security_advisories/security-advisory-tfv-9.rst
+++ b/docs/security_advisories/security-advisory-tfv-9.rst
@@ -75,7 +75,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
 +----------------------+
 | Cortex-A710          |
 +----------------------+
-| Cortex-Makalu        |
+| Cortex-A715          |
 +----------------------+
 | Cortex-Hunter        |
 +----------------------+
@@ -99,7 +99,9 @@ In case local workaround is not feasible, the Rich OS can invoke the SMC
 Convention specification`_ for more details.
 
 `Gerrit topic #spectre_bhb`_ This patchset implements the Spectre-BHB loop
-workaround for CPUs mentioned in the above table. It also mitigates against
+workaround for CPUs mentioned in the above table. For CPUs supporting
+speculative barrier instruction, the loop workaround is optimised by using SB
+in place of the common DSB and ISB sequence. It also mitigates against
 this vulnerability for Cortex-A72 CPU versions that support the CSV2 feature
 (from r1p0). The patch stack also includes an implementation for a specified
 `CVE-2022-23960`_ workaround SMC(``SMCCC_ARCH_WORKAROUND_3``) for use by normal