fix(cpus): workaround for Cortex-A710 2216384

Cortex-A710 erratum 2216384 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR5_EL1[17] to 1 and applying an instruction patching sequence.
Setting this bit, along with these instructions will prevent the
deadlock, and thereby avoids the reset of the processor.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Change-Id: I2821591c23f854c12111288ad1fd1aef45db6add
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 8a86b611cc2bd4e7df7e3a47be95edc746a42597..2c92e47aefcd8a9c24461a30db9c152177a73068 100644 (file)
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -480,6 +480,10 @@ For Cortex-A710, the following errata build flags are defined :
    Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU
    and is fixed in r2p1.
 
+-  ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
 -  ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
    of the CPU and is fixed in r2p1.

diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index 040f0737ab3485eafb22e82f45e5bb751288f4a4..e33b9d51823aead53106977743981ceb39b24024 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -42,6 +42,7 @@
  ******************************************************************************/
 #define CORTEX_A710_CPUACTLR5_EL1                              S3_0_C15_C8_0
 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13                       (ULL(1) << 13)
+#define CORTEX_A710_CPUACTLR5_EL1_BIT_17                       (ULL(1) << 17)
 #define CORTEX_A710_CPUACTLR5_EL1_BIT_44                       (ULL(1) << 44)
 
 /*******************************************************************************
@@ -52,4 +53,12 @@
 #define CPUECTLR2_EL1_PF_MODE_LSB                              U(11)
 #define CPUECTLR2_EL1_PF_MODE_WIDTH                            U(4)
 
+/*******************************************************************************
+ * CPU Selected Instruction Private register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A710_CPUPSELR_EL3                               S3_6_C15_C8_0
+#define CORTEX_A710_CPUPCR_EL3                                 S3_6_C15_C8_1
+#define CORTEX_A710_CPUPOR_EL3                                 S3_6_C15_C8_2
+#define CORTEX_A710_CPUPMR_EL3                                 S3_6_C15_C8_3
+
 #endif /* CORTEX_A710_H */

diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 0b06169ed90a79679b050cad384518497f318f36..77f7a8dd82b8ecaa2e46ab951a41c97709f54219 100644 (file)
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -311,6 +311,48 @@ func check_errata_2147715
        b       cpu_rev_var_range
 endfunc check_errata_2147715
 
+/* ---------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2216384.
+ * This applies to revision r0p0, r1p0 and r2p0.
+ * It is fixed in r2p1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------
+ */
+func errata_a710_2216384_wa
+       /* Compare x0 against revision r2p0 */
+       mov     x17, x30
+       bl      check_errata_2216384
+       cbz     x0, 1f
+
+       /* Apply workaround: set CPUACTLR5_EL1[17]
+        * to 1 and the following instruction
+        * patching sequence.
+        */
+       mrs     x1, CORTEX_A710_CPUACTLR5_EL1
+       orr     x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
+       msr     CORTEX_A710_CPUACTLR5_EL1, x1
+
+       ldr     x0,=0x5
+       msr     CORTEX_A710_CPUPSELR_EL3, x0
+       ldr     x0,=0x10F600E000
+       msr     CORTEX_A710_CPUPOR_EL3, x0
+       ldr     x0,=0x10FF80E000
+       msr     CORTEX_A710_CPUPMR_EL3, x0
+       ldr     x0,=0x80000000003FF
+       msr     CORTEX_A710_CPUPCR_EL3, x0
+       isb
+1:
+       ret     x17
+endfunc errata_a710_2216384_wa
+
+func check_errata_2216384
+       /* Applies to r0p0, r1p0 and r2p0 */
+       mov     x1, #0x20
+       b       cpu_rev_var_ls
+endfunc check_errata_2216384
+
 /* ---------------------------------------------------------------
  * Errata Workaround for Cortex-A710 Erratum 2282622.
  * This applies to revision r0p0, r1p0 and r2p0.
@@ -470,6 +512,7 @@ func cortex_a710_errata_report
        report_errata ERRATA_A710_2282622, cortex_a710, 2282622
        report_errata ERRATA_A710_2008768, cortex_a710, 2008768
        report_errata ERRATA_A710_2147715, cortex_a710, 2147715
+       report_errata ERRATA_A710_2216384, cortex_a710, 2216384
        report_errata ERRATA_A710_2371105, cortex_a710, 2371105
        report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960
        report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941
@@ -537,6 +580,11 @@ func cortex_a710_reset_func
        bl      errata_a710_2147715_wa
 #endif
 
+#if ERRATA_A710_2216384
+       mov     x0, x18
+       bl      errata_a710_2216384_wa
+#endif /* ERRATA_A710_2216384 */
+
 #if ERRATA_A710_2282622
        mov     x0, x18
        bl      errata_a710_2282622_wa
@@ -550,8 +598,8 @@ func cortex_a710_reset_func
 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
        /*
         * The Cortex-A710 generic vectors are overridden to apply errata
-         * mitigation on exception entry from lower ELs.
-         */
+        * mitigation on exception entry from lower ELs.
+        */
        adr     x0, wa_cve_vbar_cortex_a710
        msr     vbar_el3, x0
 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 9f1064a9bde253cf302ec3b9cf8ace65d5aade46..840bb4cb42d300d0df3477059c4773b013046e22 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -532,6 +532,10 @@ ERRATA_A710_2136059        ?=0
 # to revision r2p0 of the Cortex-A710 CPU and is fixed in revision r2p1.
 ERRATA_A710_2147715    ?=0
 
+# Flag to apply erratum 2216384 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
+ERRATA_A710_2216384    ?=0
+
 # Flag to apply erratum 2282622 workaround during reset. This erratum applies
 # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
 ERRATA_A710_2282622    ?=0
@@ -1119,6 +1123,10 @@ $(eval $(call add_define,ERRATA_A710_2136059))
 $(eval $(call assert_boolean,ERRATA_A710_2147715))
 $(eval $(call add_define,ERRATA_A710_2147715))
 
+# Process ERRATA_A710_2216384 flag
+$(eval $(call assert_boolean,ERRATA_A710_2216384))
+$(eval $(call add_define,ERRATA_A710_2216384))
+
 # Process ERRATA_A710_2282622 flag
 $(eval $(call assert_boolean,ERRATA_A710_2282622))
 $(eval $(call add_define,ERRATA_A710_2282622))