plat: xilinx: versal: Add support to get clock rate value

Add support to get clock's rate value.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d

diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index bb14c42e3f4e7112ff3de5fee6557822a714ec59..fd0581efaf6ff64041599ca595012411441dbbe1 100644 (file)
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -571,6 +571,22 @@ enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent)
 
        return pm_ipi_send_sync(primary_proc, payload, parent, 1);
 }
+/**
+ * pm_clock_get_rate() - Get the rate value for the clock
+ * @clk_id     Clock ID
+ * @rate:      Buffer to store clock rate value
+ *
+ * @return     Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate)
+{
+       uint32_t payload[PAYLOAD_ARG_CNT];
+
+       /* Send request to the PMC */
+       PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETRATE, clk_id);
+
+       return pm_ipi_send_sync(primary_proc, payload, clk_rate, 2);
+}
 
 /**
  * pm_pll_set_param() - Set PLL parameter
@@ -853,6 +869,7 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version)
        case PM_CLOCK_GETDIVIDER:
        case PM_CLOCK_SETPARENT:
        case PM_CLOCK_GETPARENT:
+       case PM_CLOCK_GETRATE:
        case PM_PLL_SET_PARAMETER:
        case PM_PLL_GET_PARAMETER:
        case PM_PLL_SET_MODE:

diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h
index a280b3eb07d5e4407389047ad0f19155f807c554..72f00763fb661b3c565b66571fcbb9ab453e1386 100644 (file)
--- a/plat/xilinx/versal/pm_service/pm_api_sys.h
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.h
@@ -53,6 +53,7 @@ enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider);
 enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider);
 enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent);
 enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent);
+enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate);
 enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
                                    uint32_t value);
 enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,

diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 295d1e5f6e3dcb15846f00767145493187899ec3..f2c248e15fb7ce3029a0d8f1e3f39c87c7cff39e 100644 (file)
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -264,6 +264,15 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
                SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
        }
 
+       case PM_CLOCK_GETRATE:
+       {
+               uint32_t rate[2] = { 0 };
+
+               ret = pm_clock_get_rate(pm_arg[0], rate);
+               SMC_RET2(handle, (uint64_t)ret | ((uint64_t)rate[0] << 32),
+                        rate[1]);
+       }
+
        case PM_PLL_SET_PARAMETER:
                ret = pm_pll_set_param(pm_arg[0], pm_arg[1], pm_arg[2]);
                SMC_RET1(handle, (uint64_t)ret);