Tegra186: support for the latest platform port handlers

This patch adds support for the newer platform handler functions. Commit
I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which
has already moved all the upstream supported platforms over to these
handler functions.

Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 10fea11586a474c27530598f52c0407d0d9e410e..16615a853111cd699a833726d386382b91e55588 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -37,7 +37,7 @@
  * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
  * call as the `state-id` field in the 'power state' parameter.
  ******************************************************************************/
-#define PLAT_SYS_SUSPEND_STATE_ID      0
+#define PSTATE_ID_SOC_POWERDN          1
 
 /*******************************************************************************
  * Implementation defined ACTLR_EL3 bit definitions

diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index d1e469dead2bc24e2b4e81008fc3bb5283da1555..aa4291a65b25a9c0c9684bb87e6136c16a7bd870 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -40,22 +40,28 @@
 #include <t18x_ari.h>
 #include <tegra_private.h>
 
-int32_t tegra_soc_validate_power_state(unsigned int power_state)
+int32_t tegra_soc_validate_power_state(unsigned int power_state,
+                                       psci_power_state_t *req_state)
 {
+       int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+
        /* Sanity check the requested afflvl */
        if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
                /*
                 * It's possible to enter standby only on affinity level 0 i.e.
                 * a cpu on Tegra. Ignore any other affinity level.
                 */
-               if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
+               if (pwr_lvl != MPIDR_AFFLVL0)
                        return PSCI_E_INVALID_PARAMS;
+
+               /* power domain in standby state */
+               req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE;
        }
 
        return PSCI_E_SUCCESS;
 }
 
-int tegra_soc_prepare_cpu_on(unsigned long mpidr)
+int tegra_soc_pwr_domain_on(u_register_t mpidr)
 {
        int target_cpu = mpidr & MPIDR_CPU_MASK;
        int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
@@ -74,23 +80,7 @@ int tegra_soc_prepare_cpu_on(unsigned long mpidr)
        return PSCI_E_SUCCESS;
 }
 
-int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
-{
-       /*
-        * Check if we are exiting from SOC_POWERDN.
-        */
-       if (tegra_system_suspended()) {
-
-               /*
-                * System resume complete.
-                */
-               tegra_pm_system_suspend_exit();
-       }
-
-       return PSCI_E_SUCCESS;
-}
-
-int tegra_soc_prepare_cpu_off(unsigned long mpidr)
+int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 {
        cpu_context_t *ctx = cm_get_context(NON_SECURE);
        gp_regs_t *gp_regs = get_gpregs_ctx(ctx);

diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index f88478d8b1a6aca5c2ca228b891fa65f8a4af25d..6260351190f88843445e6cc45bb5cab78cb3d79e 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -32,6 +32,23 @@
 #include <tegra_def.h>
 #include <xlat_tables.h>
 
+/*******************************************************************************
+ * The Tegra power domain tree has a single system level power domain i.e. a
+ * single root node. The first entry in the power domain descriptor specifies
+ * the number of power domains at the highest power level.
+ *******************************************************************************
+ */
+const unsigned char tegra_power_domain_tree_desc[] = {
+       /* No of root nodes */
+       1,
+       /* No of clusters */
+       PLATFORM_CLUSTER_COUNT,
+       /* No of CPU cores - cluster0 */
+       PLATFORM_MAX_CPUS_PER_CLUSTER,
+       /* No of CPU cores - cluster1 */
+       PLATFORM_MAX_CPUS_PER_CLUSTER
+};
+
 /*
  * Table of regions to map using the MMU.
  */