drm/i915/gt: Only wait for register chipset flush if active

Only serialise with the chipset using an mmio if the chipset is
currently active. We expect that any writes into the chipset range will
simply be forgotten until it wakes up.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191118184943.2593048-8-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index b5a9b87e4ec9d89fbfbb9ef995f7ef411696dd0e..c4fd8d65b8a37a87ad0b1466385a038678c82c2c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -304,7 +304,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 
        intel_gt_chipset_flush(gt);
 
-       with_intel_runtime_pm(uncore->rpm, wakeref) {
+       with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
                unsigned long flags;
 
                spin_lock_irqsave(&uncore->lock, flags);