feat(ls1046afrwy): add ls1046afrwy board support

The LS1046A Freeway board (FRWY) is a high-performance computing,
evaluation, and development platform that supports the LS1046A
architecture processor capable of support more than 32,000 CoreMark
performance. The FRWY-LS1046A board supports the LS1046A processor,
onboard DDR4 memory, multiple Gigabit Ethernet, USB3.0 and M2_Type_E
interfaces for Wi-Fi, FRWY-LS1046A-AC includes the Wi-Fi card.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a9680689e6f17bf4cc76fd5d1883eed6ace5149

diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c
new file mode 100644 (file)
index 0000000..3d561c7
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+const struct ddr_cfg_regs static_1600 = {
+       .cs[0].config = U(0x80010412),
+       .cs[0].bnds = U(0x7F),
+       .sdram_cfg[0] = U(0xE50C0008),
+       .sdram_cfg[1] = U(0x00401010),
+       .sdram_cfg[2] = U(0x1),
+       .timing_cfg[0] = U(0xFA550018),
+       .timing_cfg[1] = U(0xBAB40C52),
+       .timing_cfg[2] = U(0x0048C11C),
+       .timing_cfg[3] = U(0x01111000),
+       .timing_cfg[4] = U(0x00000002),
+       .timing_cfg[5] = U(0x03401400),
+       .timing_cfg[6] = U(0x0),
+       .timing_cfg[7] = U(0x23300000),
+       .timing_cfg[8] = U(0x02116600),
+       .timing_cfg[9] = U(0x0),
+       .dq_map[0] = U(0x0),
+       .dq_map[1] = U(0x0),
+       .dq_map[2] = U(0x0),
+       .dq_map[3] = U(0x0),
+       .sdram_mode[0] = U(0x01010210),
+       .sdram_mode[1] = U(0x0),
+       .sdram_mode[8] = U(0x00000500),
+       .sdram_mode[9] = U(0x04000000),
+       .interval = U(0x18600618),
+       .zq_cntl = U(0x8A090705),
+       .ddr_sr_cntr = U(0x0),
+       .clk_cntl = U(0x2000000),
+       .cdr[0] = U(0x80040000),
+       .cdr[1] = U(0xC1),
+       .wrlvl_cntl[0] = U(0x86550607),
+       .wrlvl_cntl[1] = U(0x07070708),
+       .wrlvl_cntl[2] = U(0x0808088),
+};
+
+long long board_static_ddr(struct ddr_info *priv)
+{
+       memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
+
+       return 0x80000000ULL;
+}
+#else /* ifndef CONFIG_STATIC_DDR */
+static const struct rc_timing rcz[] = {
+       {U(1600), U(8), U(7)},
+       {U(2100), U(8), U(7)},
+       {}
+};
+
+static const struct board_timing ram[] = {
+       {U(0x1f), rcz, U(0x01010101), U(0x01010101)},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+       int ret;
+       struct memctl_opt *popts = &priv->opt;
+
+       ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
+       if (ret != 0) {
+               return ret;
+       }
+
+       popts->bstopre = 0;
+       popts->half_strength_drive_en = 1;
+       popts->cpo_sample = U(0x46);
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_50ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_50ohm) |
+                               DDR_CDR2_VREF_TRAIN_EN;
+       popts->output_driver_impedance = 1;
+
+       return 0;
+}
+
+/* DDR model number:  MT40A512M16JY-083E:B */
+struct dimm_params ddr_raw_timing = {
+               .n_ranks = U(1),
+               .rank_density = ULL(4294967296),
+               .capacity = ULL(4294967296),
+               .primary_sdram_width = U(64),
+               .ec_sdram_width = U(8),
+               .rdimm = U(0),
+               .mirrored_dimm = U(0),
+               .n_row_addr = U(16),
+               .n_col_addr = U(10),
+               .bank_group_bits = U(1),
+               .edc_config = U(2),
+               .burst_lengths_bitmask = U(0x0c),
+               .tckmin_x_ps = 750,
+               .tckmax_ps = 1900,
+               .caslat_x = U(0x0001FFE00),
+               .taa_ps = 13500,
+               .trcd_ps = 13500,
+               .trp_ps = 13500,
+               .tras_ps = 33000,
+               .trc_ps = 46500,
+               .twr_ps = 15000,
+               .trfc1_ps = 350000,
+               .trfc2_ps = 260000,
+               .trfc4_ps = 160000,
+               .tfaw_ps = 30000,
+               .trrds_ps = 5300,
+               .trrdl_ps = 6400,
+               .tccdl_ps = 5355,
+               .refresh_rate_ps = U(7800000),
+               .dq_mapping[0] = U(0x0),
+               .dq_mapping[1] = U(0x0),
+               .dq_mapping[2] = U(0x0),
+               .dq_mapping[3] = U(0x0),
+               .dq_mapping[4] = U(0x0),
+               .dq_mapping_ors = U(0),
+               .rc = U(0x1f),
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf)
+{
+       static const char dimm_model[] = "Fixed DDR on board";
+
+       conf->dimm_in_use[0] = 1;
+       memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+       memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+       return 1;
+}
+#endif /* ifdef CONFIG_STATIC_DDR */
+
+long long init_ddr(void)
+{
+       int spd_addr[] = {NXP_SPD_EEPROM0};
+       struct ddr_info info;
+       struct sysinfo sys;
+       long long dram_size;
+
+       zeromem(&sys, sizeof(sys));
+       if (get_clocks(&sys)) {
+               ERROR("System clocks are not set\n");
+               assert(0);
+       }
+       debug("platform clock %lu\n", sys.freq_platform);
+       debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+       debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+       zeromem(&info, sizeof(struct ddr_info));
+       info.num_ctlrs = 1;
+       info.dimm_on_ctlr = 1;
+       info.clk = get_ddr_freq(&sys, 0);
+       info.spd_addr = spd_addr;
+       info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+       dram_size = dram_init(&info);
+       if (dram_size < 0) {
+               ERROR("DDR init failed.\n");
+       }
+
+#ifdef ERRATA_SOC_A008850
+       erratum_a008850_post();
+#endif
+
+       return dram_size;
+}

diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h b/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h
new file mode 100644 (file)
index 0000000..5134a00
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/*
+ * Required without TBBR.
+ * To include the defines for DDR PHY Images.
+ */
+#include <tbbr_img_def.h>
+
+#include "policy.h"
+#include <soc.h>
+
+#define NXP_SPD_EEPROM0                0x51
+
+#define NXP_SYSCLK_FREQ                100000000
+#define NXP_DDRCLK_FREQ                100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR       NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE   115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE    0x2000
+#else
+#define PLATFORM_STACK_SIZE    0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE    0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE  (0x8000)
+#define NXP_SD_BLOCK_BUF_ADDR  ULL(0x80000000)
+
+#define BL2_LIMIT              (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES         U(3)
+#define MAX_IO_BLOCK_DEVICES   U(1)
+#define MAX_IO_HANDLES         U(4)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES                U(2)
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES                U(1)
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+       INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+                       GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif /* PLAT_DEF_H */

diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c
new file mode 100644 (file)
index 0000000..cef920f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+       return true;
+#else
+       return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+       return true;
+#else
+       return false;
+#endif
+}

diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk
new file mode 100644 (file)
index 0000000..1f7fad6
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/platform.mk
@@ -0,0 +1,39 @@
+#
+# Copyright 2018-2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE      ?=      qspi
+BOARD          :=      ls1046afrwy
+POVDD_ENABLE   :=      no
+
+# DDR Compilation Configs
+CONFIG_STATIC_DDR := 0
+CONFIG_DDR_NODIMM := 1
+DDRC_NUM_DIMM  :=      0
+NUM_OF_DDRC    :=      1
+DDRC_NUM_CS    :=      1
+DDR_ECC_EN     :=      yes
+
+# On-Board Flash Details
+QSPI_FLASH_SZ  :=      0x20000000
+NOR_FLASH_SZ   :=      0x20000000
+
+# Platform specific features.
+WARM_BOOT      :=      no
+
+# Adding Platform files build files
+BL2_SOURCES    +=      ${BOARD_PATH}/ddr_init.c\
+                       ${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE    :=      qspi    \
+                               sd
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1046a/soc.mk

diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h b/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h
new file mode 100644 (file)
index 0000000..7f98bb1
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */

diff --git a/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h b/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h
new file mode 100644 (file)
index 0000000..c6c325f
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define        POLICY_H
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+#endif /* POLICY_H */