feat(mt8188): add display port control in SiP service

MTK display port mute/unmute control registers need to be
set in secure world.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0aa0675f07c80aab4349493bfbb0782bf0bbef58

diff --git a/plat/mediatek/drivers/dp/mt_dp.c b/plat/mediatek/drivers/dp/mt_dp.c
index 1bf2b444d58e37e386deb4064521f5bc6f08fe0f..8aa246f2b3bbaab65ab8d9a6ed19ea0747f7b151 100644 (file)
--- a/plat/mediatek/drivers/dp/mt_dp.c
+++ b/plat/mediatek/drivers/dp/mt_dp.c
@@ -53,7 +53,7 @@ int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
 
        if (ret == MTK_SIP_E_SUCCESS) {
                regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
-                               VIDEO_MUTE_SW_SECURE_FLDMASK);
+                         VIDEO_MUTE_SW_SECURE_FLDMASK);
                if (para > 0U) {
                        fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
                } else {
@@ -67,3 +67,13 @@ int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
 
        return ret;
 }
+
+u_register_t mtk_dp_sip_handler(u_register_t x1, u_register_t x2,
+                               u_register_t x3, u_register_t x4,
+                               void *handle, struct smccc_res *smccc_ret)
+{
+       uint32_t ret_val;
+
+       return dp_secure_handler(x1, x2, &ret_val);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_DP_CONTROL, mtk_dp_sip_handler);

diff --git a/plat/mediatek/include/mt8188/platform_def.h b/plat/mediatek/include/mt8188/platform_def.h
index 88a9e46e305e74ff858363d382ffc4c2c64402ab..15ea5b63aac8e425e6efb4ac5ff328144fcfa149 100644 (file)
--- a/plat/mediatek/include/mt8188/platform_def.h
+++ b/plat/mediatek/include/mt8188/platform_def.h
@@ -41,6 +41,14 @@
 #define CIRQ_REG_NUM           (23)
 #define CIRQ_SPI_START         (96)
 
+/*******************************************************************************
+ * DP related constants
+ ******************************************************************************/
+#define EDP_SEC_BASE           (IO_PHYS + 0x0C504000)
+#define DP_SEC_BASE            (IO_PHYS + 0x0C604000)
+#define EDP_SEC_SIZE           (0x1000)
+#define DP_SEC_SIZE            (0x1000)
+
 /*******************************************************************************
  * System counter frequency related constants
  ******************************************************************************/

diff --git a/plat/mediatek/include/mtk_sip_def.h b/plat/mediatek/include/mtk_sip_def.h
index b591499a55447f7bd475e5e61915b466ea84115f..37734eaa18f1404be09a4dc74c8f01e49819922c 100644 (file)
--- a/plat/mediatek/include/mtk_sip_def.h
+++ b/plat/mediatek/include/mtk_sip_def.h
@@ -12,6 +12,7 @@
        _func(MTK_SIP_KERNEL_TIME_SYNC, 0x202) \
        _func(MTK_SIP_VCORE_CONTROL, 0x506) \
        _func(MTK_SIP_APUSYS_CONTROL, 0x51E) \
+       _func(MTK_SIP_DP_CONTROL, 0x523) \
        _func(MTK_SIP_KERNEL_GIC_OP, 0x526)
 
 #define MTK_SIP_SMC_FROM_BL33_TABLE(_func) \

diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
index 83a5b95bdcc28afe68e0a680f9b8b30fb13318ca..61b61dbe0452c52cfa4f05f08e5e2a570c4a39e5 100644 (file)
--- a/plat/mediatek/mt8188/platform.mk
+++ b/plat/mediatek/mt8188/platform.mk
@@ -23,6 +23,7 @@ MODULES-y += $(MTK_PLAT)/common
 MODULES-y += $(MTK_PLAT)/lib/mtk_init
 MODULES-y += $(MTK_PLAT)/lib/pm
 MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/dp
 MODULES-y += $(MTK_PLAT)/drivers/gic600
 MODULES-y += $(MTK_PLAT)/drivers/timer