net/mlx5: Unify device IPsec capabilities check
authorLeon Romanovsky <leonro@nvidia.com>
Wed, 6 Apr 2022 08:25:46 +0000 (11:25 +0300)
committerLeon Romanovsky <leonro@nvidia.com>
Sat, 9 Apr 2022 05:25:07 +0000 (08:25 +0300)
Merge two different function to one in order to provide coherent
picture if the device is IPsec capable or not.

Link: https://lore.kernel.org/r/8f10ea06ad19c6f651e9fb33921009658f01e1d5.1649232994.git.leonro@nvidia.com
Reviewed-by: Raed Salem <raeds@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec_offload.c
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec_offload.h
drivers/net/ethernet/mellanox/mlx5/core/en/params.c
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
include/linux/mlx5/accel.h

index 3a85157f9f076cda2596477319b1688ff0572de3..9dbebef19ff044f76579194f15a9a0ceefceba25 100644 (file)
@@ -6,9 +6,6 @@
 #include "lib/mlx5.h"
 #include "en_accel/ipsec_fs.h"
 
-#define MLX5_IPSEC_DEV_BASIC_CAPS (MLX5_ACCEL_IPSEC_CAP_DEVICE | MLX5_ACCEL_IPSEC_CAP_IPV6 | \
-                                  MLX5_ACCEL_IPSEC_CAP_LSO)
-
 struct mlx5_ipsec_sa_ctx {
        struct rhash_head hash;
        u32 enc_key_id;
@@ -25,17 +22,31 @@ struct mlx5_ipsec_esp_xfrm {
        struct mlx5_accel_esp_xfrm accel_xfrm;
 };
 
-static u32 mlx5_ipsec_offload_device_caps(struct mlx5_core_dev *mdev)
+u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
 {
-       u32 caps = MLX5_IPSEC_DEV_BASIC_CAPS;
+       u32 caps;
+
+       if (!MLX5_CAP_GEN(mdev, ipsec_offload))
+               return 0;
+
+       if (!MLX5_CAP_GEN(mdev, log_max_dek))
+               return 0;
+
+       if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
+           MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC))
+               return 0;
 
-       if (!mlx5_is_ipsec_device(mdev))
+       if (!MLX5_CAP_IPSEC(mdev, ipsec_crypto_offload) ||
+           !MLX5_CAP_ETH(mdev, insert_trailer))
                return 0;
 
        if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ipsec_encrypt) ||
            !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ipsec_decrypt))
                return 0;
 
+       caps = MLX5_ACCEL_IPSEC_CAP_DEVICE | MLX5_ACCEL_IPSEC_CAP_IPV6 |
+              MLX5_ACCEL_IPSEC_CAP_LSO;
+
        if (MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_encrypt) &&
            MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_decrypt))
                caps |= MLX5_ACCEL_IPSEC_CAP_ESP;
@@ -52,6 +63,7 @@ static u32 mlx5_ipsec_offload_device_caps(struct mlx5_core_dev *mdev)
        WARN_ON_ONCE(MLX5_CAP_IPSEC(mdev, log_max_ipsec_offload) > 24);
        return caps;
 }
+EXPORT_SYMBOL_GPL(mlx5_ipsec_device_caps);
 
 static int
 mlx5_ipsec_offload_esp_validate_xfrm_attrs(struct mlx5_core_dev *mdev,
@@ -367,7 +379,6 @@ change_sw_xfrm_attrs:
 }
 
 static const struct mlx5_accel_ipsec_ops ipsec_offload_ops = {
-       .device_caps = mlx5_ipsec_offload_device_caps,
        .create_hw_context = mlx5_ipsec_offload_create_sa_ctx,
        .free_hw_context = mlx5_ipsec_offload_delete_sa_ctx,
        .init = mlx5_ipsec_offload_init,
@@ -379,7 +390,7 @@ static const struct mlx5_accel_ipsec_ops ipsec_offload_ops = {
 static const struct mlx5_accel_ipsec_ops *
 mlx5_ipsec_offload_ops(struct mlx5_core_dev *mdev)
 {
-       if (!mlx5_ipsec_offload_device_caps(mdev))
+       if (!mlx5_ipsec_device_caps(mdev))
                return NULL;
 
        return &ipsec_offload_ops;
@@ -416,17 +427,6 @@ void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
        ipsec_ops->cleanup(mdev);
 }
 
-u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
-{
-       const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
-
-       if (!ipsec_ops || !ipsec_ops->device_caps)
-               return 0;
-
-       return ipsec_ops->device_caps(mdev);
-}
-EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps);
-
 unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
 {
        const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
index 4a7d49ed5604ad9f58fcf71fc29b3d85f46302b3..3d13e2c136b166d26470c87e627bfc61dc452552 100644 (file)
@@ -9,9 +9,6 @@
 
 #ifdef CONFIG_MLX5_IPSEC
 
-#define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \
-                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
-
 unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev);
 int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
                                   unsigned int count);
@@ -25,7 +22,6 @@ void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev);
 void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev);
 
 struct mlx5_accel_ipsec_ops {
-       u32 (*device_caps)(struct mlx5_core_dev *mdev);
        unsigned int (*counters_count)(struct mlx5_core_dev *mdev);
        int (*counters_read)(struct mlx5_core_dev *mdev, u64 *counters,
                             unsigned int count);
@@ -45,25 +41,8 @@ struct mlx5_accel_ipsec_ops {
        void (*esp_destroy_xfrm)(struct mlx5_accel_esp_xfrm *xfrm);
 };
 
-static inline bool mlx5_is_ipsec_device(struct mlx5_core_dev *mdev)
-{
-       if (!MLX5_CAP_GEN(mdev, ipsec_offload))
-               return false;
-
-       if (!MLX5_CAP_GEN(mdev, log_max_dek))
-               return false;
-
-       if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
-           MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC))
-               return false;
-
-       return MLX5_CAP_IPSEC(mdev, ipsec_crypto_offload) &&
-               MLX5_CAP_ETH(mdev, insert_trailer);
-}
 #else
 
-#define MLX5_IPSEC_DEV(mdev) false
-
 static inline void *
 mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
                                 struct mlx5_accel_esp_xfrm *xfrm,
@@ -80,10 +59,5 @@ static inline void mlx5_accel_esp_free_hw_context(struct mlx5_core_dev *mdev,
 static inline void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev) {}
 
 static inline void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev) {}
-static inline bool mlx5_is_ipsec_device(struct mlx5_core_dev *mdev)
-{
-       return false;
-}
-
 #endif /* CONFIG_MLX5_IPSEC */
 #endif /* __MLX5_IPSEC_OFFLOAD_H__ */
index d2ec0961fe9ecb5439cbe19106c19a532bfd1d65..9f4ae8bc09b99e0b5590da44bb178ba6ab054d13 100644 (file)
@@ -689,8 +689,8 @@ void mlx5e_build_sq_param(struct mlx5_core_dev *mdev,
        void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
        bool allow_swp;
 
-       allow_swp = mlx5_geneve_tx_allowed(mdev) ||
-                   !!MLX5_IPSEC_DEV(mdev);
+       allow_swp =
+               mlx5_geneve_tx_allowed(mdev) || !!mlx5_ipsec_device_caps(mdev);
        mlx5e_build_sq_param_common(mdev, param);
        MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
        MLX5_SET(sqc, sqc, allow_swp, allow_swp);
index 1391a0c84f16727ef828f99c4b1be58fc1997768..c280a18ff0027d677ec17d8a80f7dbd4246a4686 100644 (file)
@@ -226,8 +226,7 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x)
                return -EINVAL;
        }
        if (x->props.flags & XFRM_STATE_ESN &&
-           !(mlx5_accel_ipsec_device_caps(priv->mdev) &
-           MLX5_ACCEL_IPSEC_CAP_ESN)) {
+           !(mlx5_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_CAP_ESN)) {
                netdev_info(netdev, "Cannot offload ESN xfrm states\n");
                return -EINVAL;
        }
@@ -275,8 +274,7 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x)
                return -EINVAL;
        }
        if (x->props.family == AF_INET6 &&
-           !(mlx5_accel_ipsec_device_caps(priv->mdev) &
-            MLX5_ACCEL_IPSEC_CAP_IPV6)) {
+           !(mlx5_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_CAP_IPV6)) {
                netdev_info(netdev, "IPv6 xfrm state offload is not supported by this device\n");
                return -EINVAL;
        }
@@ -406,7 +404,7 @@ int mlx5e_ipsec_init(struct mlx5e_priv *priv)
 {
        struct mlx5e_ipsec *ipsec = NULL;
 
-       if (!MLX5_IPSEC_DEV(priv->mdev)) {
+       if (!mlx5_ipsec_device_caps(priv->mdev)) {
                netdev_dbg(priv->netdev, "Not an IPSec offload device\n");
                return 0;
        }
@@ -519,7 +517,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv)
        struct mlx5_core_dev *mdev = priv->mdev;
        struct net_device *netdev = priv->netdev;
 
-       if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_ESP) ||
+       if (!(mlx5_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_ESP) ||
            !MLX5_CAP_ETH(mdev, swp)) {
                mlx5_core_dbg(mdev, "mlx5e: ESP and SWP offload not supported\n");
                return;
@@ -538,7 +536,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv)
        netdev->features |= NETIF_F_HW_ESP_TX_CSUM;
        netdev->hw_enc_features |= NETIF_F_HW_ESP_TX_CSUM;
 
-       if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_LSO) ||
+       if (!(mlx5_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_LSO) ||
            !MLX5_CAP_ETH(mdev, swp_lso)) {
                mlx5_core_dbg(mdev, "mlx5e: ESP LSO not supported\n");
                return;
index 346f7034fec8e12bc28729a83c49fcc347bf9138..6a3a08fd89104ebbc9a89ea9f408aa1dec177ca6 100644 (file)
@@ -1329,7 +1329,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
        INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
        if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
                set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
-       if (MLX5_IPSEC_DEV(c->priv->mdev))
+       if (mlx5_ipsec_device_caps(c->priv->mdev))
                set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
        if (param->is_mpw)
                set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
index af67d51308cf84fd391ac0d79da8d1b7f011b3ca..9145e2d37c0e85c70518614f25d8dbc65c0598c5 100644 (file)
@@ -124,7 +124,7 @@ enum mlx5_accel_ipsec_cap {
 
 #ifdef CONFIG_MLX5_ACCEL
 
-u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
+u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev);
 
 struct mlx5_accel_esp_xfrm *
 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
@@ -135,7 +135,10 @@ int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
 
 #else
 
-static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
+static inline u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
+{
+       return 0;
+}
 
 static inline struct mlx5_accel_esp_xfrm *
 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,