refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs

The DT files for the Cortex-A5 and Cortex-A7 FVP models include the
shared rtsm_ve-motherboard.dtsi file, which we need to sync with the
upstream Linux version soon.

To prepare for its changed structure there, adjust the top-level
 #address-cells and #size-cells properties to be compatible with the
expectations of the Linux version.
Also extend the interrupt map to cover all peripherals listed in the
motherboard file, and use the proper GIC macros to make them more
readable on the way.

Change-Id: I7d1493f1a200e8350530f912833f9ffcc5f94b21
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/fdts/fvp-ve-Cortex-A5x1.dts b/fdts/fvp-ve-Cortex-A5x1.dts
index 9d2d1d552d255158de7792b6e37f4ad7a303289a..f44a7d12dc59225510d69c08dee5b1079b7a8acb 100644 (file)
--- a/fdts/fvp-ve-Cortex-A5x1.dts
+++ b/fdts/fvp-ve-Cortex-A5x1.dts
@@ -1,16 +1,18 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /dts-v1/;
 
 / {
        model = "V2P-CA5s";
        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
        interrupt-parent = <&gic>;
-       #address-cells = <1>;
+       #address-cells = <2>;
        #size-cells = <1>;
 
        cpus {
@@ -27,12 +29,12 @@
 
        memory@80000000 {
                device_type = "memory";
-               reg = <0x80000000 0x1000000>;
+               reg = <0 0x80000000 0x1000000>;
        };
 
        hdlcd@2a110000 {
                compatible = "arm,hdlcd";
-               reg = <0x2a110000 0x1000>;
+               reg = <0 0x2a110000 0x1000>;
                interrupts = <0 85 4>;
                clocks = <&oscclk3>;
                clock-names = "pxlclk";
@@ -40,12 +42,12 @@
 
        scu@2c000000 {
                compatible = "arm,cortex-a5-scu";
-               reg = <0x2c000000 0x58>;
+               reg = <0 0x2c000000 0x58>;
        };
 
        watchdog@2c000620 {
                compatible = "arm,cortex-a5-twd-wdt";
-               reg = <0x2c000620 0x20>;
+               reg = <0 0x2c000620 0x20>;
                interrupts = <1 14 0x304>;
        };
 
@@ -54,8 +56,8 @@
                #interrupt-cells = <3>;
                #address-cells = <0>;
                interrupt-controller;
-               reg = <0x2c001000 0x1000>,
-                     <0x2c000100 0x100>;
+               reg = <0 0x2c001000 0x1000>,
+                     <0 0x2c000100 0x100>;
        };
 
        dcc {
@@ -122,22 +124,34 @@
 
                #address-cells = <2>;
                #size-cells = <1>;
-               ranges = <0 0 0x08000000 0x04000000>,
-                        <1 0 0x14000000 0x04000000>,
-                        <2 0 0x18000000 0x04000000>,
-                        <3 0 0x1c000000 0x04000000>,
-                        <4 0 0x0c000000 0x04000000>,
-                        <5 0 0x10000000 0x04000000>;
+               ranges = <0 0 0 0x08000000 0x04000000>,
+                        <1 0 0 0x14000000 0x04000000>,
+                        <2 0 0 0x18000000 0x04000000>,
+                        <3 0 0 0x1c000000 0x04000000>,
+                        <4 0 0 0x0c000000 0x04000000>,
+                        <5 0 0 0x10000000 0x04000000>;
 
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
-               interrupt-map = <0 0  0 &gic 0  0 4>,
-                               <0 0  1 &gic 0  1 4>,
-                               <0 0  2 &gic 0  2 4>,
-                               <0 0  3 &gic 0  3 4>,
-                               <0 0  4 &gic 0  4 4>,
-                               <0 0  5 &gic 0  5 4>,
-                               <0 0 42 &gic 0 42 4>;
+               interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 
                #include "rtsm_ve-motherboard-aarch32.dtsi"
        };

diff --git a/fdts/fvp-ve-Cortex-A7x1.dts b/fdts/fvp-ve-Cortex-A7x1.dts
index 28de91d3c86e5a875b2ea0b393e94f97250e81aa..99af665295a69adda989259217af980de5876846 100644 (file)
--- a/fdts/fvp-ve-Cortex-A7x1.dts
+++ b/fdts/fvp-ve-Cortex-A7x1.dts
@@ -1,9 +1,11 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /dts-v1/;
 
 / {
@@ -11,22 +13,22 @@
        compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <2>;
-       #size-cells = <2>;
+       #size-cells = <1>;
 
        cpus {
-               #address-cells = <2>;
+               #address-cells = <1>;
                #size-cells = <0>;
 
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
-                       reg = <0 0>;
+                       reg = <0>;
                };
        };
 
        memory@0,80000000 {
                device_type = "memory";
-               reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
+               reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */
        };
 
        gic: interrupt-controller@2c001000 {
@@ -34,10 +36,10 @@
                #interrupt-cells = <3>;
                #address-cells = <0>;
                interrupt-controller;
-               reg = <0 0x2c001000 0 0x1000>,
-                     <0 0x2c002000 0 0x1000>,
-                     <0 0x2c004000 0 0x2000>,
-                     <0 0x2c006000 0 0x2000>;
+               reg = <0 0x2c001000 0x1000>,
+                     <0 0x2c002000 0x1000>,
+                     <0 0x2c004000 0x2000>,
+                     <0 0x2c006000 0x2000>;
                interrupts = <1 9 0xf04>;
        };
 
@@ -63,13 +65,25 @@
 
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
-               interrupt-map = <0 0  0 &gic 0  0 4>,
-                               <0 0  1 &gic 0  1 4>,
-                               <0 0  2 &gic 0  2 4>,
-                               <0 0  3 &gic 0  3 4>,
-                               <0 0  4 &gic 0  4 4>,
-                               <0 0  5 &gic 0  5 4>,
-                               <0 0 42 &gic 0 42 4>;
+               interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                               <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 
                #include "rtsm_ve-motherboard-aarch32.dtsi"
        };