arm64: dts: freescale: Fix SP805 clock-names

[ Upstream commit 6a2548c409727707fd3a78ab080654ffff6fbbcc ]

The SP805 binding sets the order of the clock-names to be: "wdog_clk",
"apb_pclk" (in exactly that order).

Change the order in the DTs for Freescale platforms to match that. The
two clocks given in all nodes are actually the same, so that does not
change any behaviour.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 5716ac20bddd112e549a75d10109dcb1c284232c..963091069ab30c917bc07b4d1155dd6ef3d9d1c0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -496,14 +496,14 @@
                        compatible = "arm,sp805", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 15>, <&clockgen 4 15>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: watchdog@c010000 {
                        compatible = "arm,sp805", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 15>, <&clockgen 4 15>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                sai1: audio-controller@f100000 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index c676d0771762fcbc69c96f3f05b693b0909836e1..407ebdb35cd2e9a164b294839ffe62c48be6da68 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -640,56 +640,56 @@
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: wdt@c010000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core2_watchdog: wdt@c020000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc020000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core3_watchdog: wdt@c030000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc030000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core0_watchdog: wdt@c100000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc100000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core1_watchdog: wdt@c110000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc110000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core2_watchdog: wdt@c120000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc120000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core3_watchdog: wdt@c130000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc130000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                fsl_mc: fsl-mc@80c000000 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index cdb2fa47637daa3fc5054159c9373a23cdcfd31f..82f0fe6acbfb75bac30cd6cfa1d82b214f007767 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -230,56 +230,56 @@
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: wdt@c010000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core0_watchdog: wdt@c100000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc100000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core1_watchdog: wdt@c110000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc110000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster3_core0_watchdog: wdt@c200000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc200000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster3_core1_watchdog: wdt@c210000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc210000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster4_core0_watchdog: wdt@c300000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc300000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster4_core1_watchdog: wdt@c310000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc310000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                crypto: crypto@8000000 {