}
args_mapping_size = ALIGNED_UP(sizeof(struct_drtm_dl_args), DRTM_PAGE_SIZE);
+
+ /* check DRTM parameters are within NS address region */
+ rc = plat_drtm_validate_ns_region(x1, args_mapping_size);
+ if (rc != 0) {
+ ERROR("DRTM: parameters lies within secure memory\n");
+ return INVALID_PARAMETERS;
+ }
+
rc = mmap_add_dynamic_region_alloc_va(x1, &args_mapping, args_mapping_size,
MT_MEMORY | MT_NS | MT_RO |
MT_SHAREABILITY_ISH);
dlme_data_start = a->dlme_paddr + a->dlme_data_off;
dlme_data_end = dlme_end;
- /*
- * TODO: validate that the DLME physical address range is all NS memory,
- * return INVALID_PARAMETERS if it is not.
- * Note that this check relies on platform-specific information. For
- * examples, see psci_plat_pm_ops->validate_ns_entrypoint() or
- * arm_validate_ns_entrypoint().
- */
-
/* Check the DLME regions arguments. */
if ((dlme_start % DRTM_PAGE_SIZE) != 0) {
ERROR("DRTM: argument DLME region is not "
return INVALID_PARAMETERS;
}
+ /* check DLME region (paddr + size) is within a NS address region */
+ rc = plat_drtm_validate_ns_region(dlme_start, (size_t)a->dlme_size);
+ if (rc != 0) {
+ ERROR("DRTM: DLME region lies within secure memory\n");
+ return INVALID_PARAMETERS;
+ }
+
/* Check the Normal World DCE region arguments. */
if (a->dce_nwd_paddr != 0) {
uint32_t dce_nwd_start = a->dce_nwd_paddr;