powerpc/32: transfer can avoid saving r4/r5 over trace call

Now that handlers get all registers from pt_regs, r4 and r5 are no
longer live here and may be clobbered.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210130130852.2952424-11-npiggin@gmail.com

diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 238eacfda7b05792be38fd75fcde443ebe0c2a59..d6ea3f2d6cc083fd9a6bc4a9cbff2f98fdc7c49e 100644 (file)
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -276,8 +276,7 @@ reenable_mmu:
         * We save a bunch of GPRs,
         * r3 can be different from GPR3(r1) at this point, r9 and r11
         * contains the old MSR and handler address respectively,
-        * r4 & r5 can contain page fault arguments that need to be passed
-        * along as well. r0, r6-r8, r12, CCR, CTR, XER etc... are left
+        * r0, r4-r8, r12, CCR, CTR, XER etc... are left
         * clobbered as they aren't useful past this point.
         */
 
@@ -285,15 +284,11 @@ reenable_mmu:
        stw     r9,8(r1)
        stw     r11,12(r1)
        stw     r3,16(r1)
-       stw     r4,20(r1)
-       stw     r5,24(r1)
 
        /* If we are disabling interrupts (normal case), simply log it with
         * lockdep
         */
 1:     bl      trace_hardirqs_off
-       lwz     r5,24(r1)
-       lwz     r4,20(r1)
        lwz     r3,16(r1)
        lwz     r11,12(r1)
        lwz     r9,8(r1)