/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x440
-#define PLATFORM_CORE_COUNT 2
+#define PLATFORM_CORE_COUNT U(2)
#define PLAT_MAX_PWR_LVL 1
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 2
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x440
-#define PLATFORM_CORE_COUNT 4
-#define PLAT_NUM_POWER_DOMAINS 5
+#define PLATFORM_CORE_COUNT U(4)
+#define PLAT_NUM_POWER_DOMAINS U(5)
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(2)