obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
- obj-$(CONFIG_STM32H7) += clk_stm32h7.o
- obj-$(CONFIG_CLK_BAIKAL) += clk_baikal.o
++obj-$(CONFIG_CLK_BAIKAL) += clk_baikal.o
help
Support CPU cores for RISC-V architecture.
++<<<<<<< HEAD
+config CPU_BAIKAL
+ bool "Enable Baikal-T1 CPU driver"
+ depends on CPU
+ help
+ Support CPU cores for Baikal mips chips.
++=======
+ config CPU_MICROBLAZE
+ bool "Enable Microblaze CPU driver"
+ depends on CPU && MICROBLAZE
+ select DM_EVENT
+ select XILINX_MICROBLAZE0_PVR
+ help
+ Support CPU cores for Microblaze architecture.
++>>>>>>> upstream_testing
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
+ obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
+obj-$(CONFIG_CPU_BAIKAL) += baikal_cpu.o
+ obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
struct dmamacdescr *desc_p;
u32 idx;
- for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+ for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = virt_to_phys(&txbuffs[idx * CONFIG_ETH_BUFSIZE]);
- desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE];
- desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
++ desc_p->dmamac_addr = virt_to_phys(&txbuffs[idx * CFG_ETH_BUFSIZE]);
+ desc_p->dmamac_next = virt_to_phys(&desc_table_p[idx + 1]);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
* GMAC data will be corrupted. */
flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
- for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+ for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = virt_to_phys(&rxbuffs[idx * CONFIG_ETH_BUFSIZE]);
- desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE];
- desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
-
++ desc_p->dmamac_addr = virt_to_phys(&rxbuffs[idx * CFG_ETH_BUFSIZE]);
+ desc_p->dmamac_next = virt_to_phys(&desc_table_p[idx + 1]);
-
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
DESC_RXCTRL_RXCHAIN;
struct phy_device *phydev;
struct mii_dev *bus;
+ u32 flags;
+#define DWMAC_PHY_RESET 1
+#define DWMAC_PHY_RECONFIG 2
};
- #ifdef CONFIG_DM_ETH
int designware_eth_of_to_plat(struct udevice *dev);
int designware_eth_probe(struct udevice *dev);
extern const struct eth_ops designware_eth_ops;
Say Y here if you want to enable PCIe controller support on
FU740.
+config PCIE_DW_GENERIC
+ bool "Enable generic DesignWare PCIe driver"
+ help
+ Say Y here if you want to enable PCIe controller support on
+ DesignWare hardware.
+
+ config SYS_FSL_PCI_VER_3_X
+ bool
+
config PCIE_FSL
bool "FSL PowerPC PCIe support"
+ select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240
help
Say Y here if you want to enable PCIe controller support on FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
#include <image.h>
#include <version.h>
+/*
#include <openssl/pem.h>
#include <openssl/evp.h>
+*/
- #define IMAGE_PRE_LOAD_PATH "/image/pre-load/sig"
-
/**
* fit_set_hash_value - set hash value in requested has node
* @fit: pointer to the FIT format image header