#define ESR_ELx_CV (UL(1) << 24)
#define ESR_ELx_COND_SHIFT (20)
#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
- #define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
+ #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
+ #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
+ #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
+ #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
-#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
+#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
#define DISR_EL1_IDS (UL(1) << 24)
/*