Tegra186: register FIQ interrupt sources

This patch registers all the FIQ interrupt sources during platform
setup. Currently we support AON and TOP watchdog timer interrupts.

Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index e74ed166fe63cc84095f0d03c25ad98da8ad11a6..0732993d903aaa5af1602cc5e76be1a9fd1e4f9d 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -65,6 +65,14 @@
                                         ACTLR_EL3_CPUECTLR_BIT | \
                                         ACTLR_EL3_CPUACTLR_BIT)
 
+/*******************************************************************************
+ * Secure IRQ definitions
+ ******************************************************************************/
+#define TEGRA186_TOP_WDT_IRQ           49
+#define TEGRA186_AON_WDT_IRQ           50
+
+#define TEGRA186_SEC_IRQ_TARGET_MASK   0xF3 /* 4 A57 - 2 Denver */
+
 /*******************************************************************************
  * Tegra Miscellanous register constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 0496f5a5e5ed7131ff0a0e45d6c6485e2dcf5deb..44faefef076ac4a62ffbcee3e3d35ddc8bf5f3c4 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -28,8 +28,18 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <arch_helpers.h>
+#include <assert.h>
+#include <bl_common.h>
 #include <console.h>
+#include <context.h>
+#include <context_mgmt.h>
+#include <debug.h>
+#include <denver.h>
+#include <interrupt_mgmt.h>
+#include <platform.h>
 #include <tegra_def.h>
+#include <tegra_private.h>
 #include <xlat_tables.h>
 
 /*******************************************************************************
@@ -120,3 +130,33 @@ uint32_t plat_get_console_from_id(int id)
 
        return tegra186_uart_addresses[id];
 }
+
+/* Secure IRQs for Tegra186 */
+static const irq_sec_cfg_t tegra186_sec_irqs[] = {
+       {
+               TEGRA186_TOP_WDT_IRQ,
+               TEGRA186_SEC_IRQ_TARGET_MASK,
+               INTR_TYPE_EL3,
+       },
+       {
+               TEGRA186_AON_WDT_IRQ,
+               TEGRA186_SEC_IRQ_TARGET_MASK,
+               INTR_TYPE_EL3,
+       },
+};
+
+/*******************************************************************************
+ * Initialize the GIC and SGIs
+ ******************************************************************************/
+void plat_gic_setup(void)
+{
+       tegra_gic_setup(tegra186_sec_irqs,
+               sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
+
+       /*
+        * Initialize the FIQ handler only if the platform supports any
+        * FIQ interrupt sources.
+        */
+       if (sizeof(tegra186_sec_irqs) > 0)
+               tegra_fiq_handler_setup();
+}

diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index 66a433e94aae2dca9f5a9cc981707c3569494812..8b340a19075a0709a282c82b187610eb4f093e37 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -134,7 +134,6 @@ int plat_sip_handler(uint32_t smc_fid,
                return 0;
 
        default:
-               ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
                break;
        }