allwinner: Add SPC security setup for H6

The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5

diff --git a/plat/allwinner/common/sunxi_security.c b/plat/allwinner/common/sunxi_security.c
index fab3ba81a62d72b77d73ee352c061c469da2784b..98b91c39f6c8b7cd1e168433659efbeb7482ed48 100644 (file)
--- a/plat/allwinner/common/sunxi_security.c
+++ b/plat/allwinner/common/sunxi_security.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,12 +10,7 @@
 #include <sunxi_ccu.h>
 #include <sunxi_mmap.h>
 #include <sunxi_private.h>
-
-#ifdef SUNXI_SPC_BASE
-#define SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4)
-#define SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8)
-#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
-#endif
+#include <sunxi_spc.h>
 
 #define DMA_SEC_REG            0x20
 
@@ -27,14 +22,12 @@
  */
 void sunxi_security_setup(void)
 {
-#ifdef SUNXI_SPC_BASE
        int i;
 
        INFO("Configuring SPC Controller\n");
        /* SPC setup: set all devices to non-secure */
-       for (i = 0; i < 6; i++)
-               mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
-#endif
+       for (i = 0; i < SUNXI_SPC_NUM_PORTS; i++)
+               mmio_write_32(SUNXI_SPC_DECPORT_SET_REG(i), 0xffffffff);
 
        /* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
        mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);

diff --git a/plat/allwinner/sun50i_a64/include/sunxi_spc.h b/plat/allwinner/sun50i_a64/include/sunxi_spc.h
new file mode 100644 (file)
index 0000000..5ba7e18
--- /dev/null
+++ b/plat/allwinner/sun50i_a64/include/sunxi_spc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+#define SUNXI_SPC_NUM_PORTS            6
+
+#define SUNXI_SPC_DECPORT_STA_REG(p)   (SUNXI_SPC_BASE + 0x0004 + 0x0c * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p)   (SUNXI_SPC_BASE + 0x0008 + 0x0c * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p)   (SUNXI_SPC_BASE + 0x000c + 0x0c * (p))
+
+#endif /* SUNXI_SPC_H */

diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
index 39a505a818d1ead59fb4a64b19ca64c06036f096..514621f00b766802b1d0eb6cc4ba83a3efdf9ebe 100644 (file)
--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -31,6 +31,7 @@
 #define SUNXI_MSGBOX_BASE              0x03003000
 #define SUNXI_CCU_BASE                 0x03001000
 #define SUNXI_PIO_BASE                 0x0300b000
+#define SUNXI_SPC_BASE                 0x03008000
 #define SUNXI_TIMER_BASE               0x03009000
 #define SUNXI_WDOG_BASE                        0x030090a0
 #define SUNXI_THS_BASE                 0x05070400

diff --git a/plat/allwinner/sun50i_h6/include/sunxi_spc.h b/plat/allwinner/sun50i_h6/include/sunxi_spc.h
new file mode 100644 (file)
index 0000000..0f5965b
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/include/sunxi_spc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+#define SUNXI_SPC_NUM_PORTS            14
+
+#define SUNXI_SPC_DECPORT_STA_REG(p)   (SUNXI_SPC_BASE + 0x0000 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p)   (SUNXI_SPC_BASE + 0x0004 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p)   (SUNXI_SPC_BASE + 0x0008 + 0x10 * (p))
+
+#endif /* SUNXI_SPC_H */