--- /dev/null
+/*
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_SHARED_RESOURCES_H
+#define STM32MP_SHARED_RESOURCES_H
+
+#include <stdbool.h>
+
+/* Return true if @clock_id is shared by secure and non-secure worlds */
+bool stm32mp_nsec_can_access_clock(unsigned long clock_id);
+
+/* Return true if and only if @reset_id relates to a non-secure peripheral */
+bool stm32mp_nsec_can_access_reset(unsigned int reset_id);
+
+#endif /* STM32MP_SHARED_RESOURCES_H */
SP_MIN_WITH_SECURE_FIQ := 1
+BL32_CFLAGS += -DSTM32MP_SHARED_RESOURCES
+
BL32_SOURCES += drivers/st/etzpc/etzpc.c \
plat/common/aarch32/platform_mp_stack.S \
plat/st/stm32mp1/sp_min/sp_min_setup.c \
plat/st/stm32mp1/stm32mp1_pm.c \
+ plat/st/stm32mp1/stm32mp1_shared_resources.c \
plat/st/stm32mp1/stm32mp1_topology.c
# Generic GIC v2
--- /dev/null
+/*
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stm32mp_shared_resources.h>
+
+/* Currently allow full access by non-secure to platform clock services */
+bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
+{
+ return true;
+}
+
+/* Currently allow full access by non-secure to platform reset services */
+bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
+{
+ return true;
+}