uniphier: make UART base address configurable

The next SoC supports the same UART, but the register base will be
changed. Make it configurable.

Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
index 4f58b683c8b0738d0c45d41f0ac0c273fdfedb81..5ea6e9474c1df08af97a71767891074379b447b1 100644 (file)
--- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
+++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
@@ -4,16 +4,25 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <errno.h>
+
 #include <platform_def.h>
 
 #include <common/bl_common.h>
 #include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <plat/common/platform.h>
 
 #include "../uniphier.h"
 
+static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
+
 void tsp_early_platform_setup(void)
 {
-       uniphier_console_setup();
+       uniphier_soc = uniphier_get_soc_id();
+       if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
+               plat_error_handler(-ENOTSUP);
+
+       uniphier_console_setup(uniphier_soc);
 }
 
 void tsp_platform_setup(void)

diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h
index 808b850d66054769d87b2f40762894a0931bceab..f8aa65ab7222c7a61a9e84d5fcd47ce2e4bed1ee 100644 (file)
--- a/plat/socionext/uniphier/uniphier.h
+++ b/plat/socionext/uniphier/uniphier.h
@@ -35,7 +35,7 @@ unsigned int uniphier_get_boot_master(unsigned int soc);
 #define UNIPHIER_BOOT_MASTER_SCP       1
 #define UNIPHIER_BOOT_MASTER_EXT       2
 
-void uniphier_console_setup(void);
+void uniphier_console_setup(unsigned int soc);
 
 struct io_block_dev_spec;
 int uniphier_emmc_init(unsigned int soc,

diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c
index 11d837cf4f49f2f5a7b45a66f45a73293d2b1fb3..9c8d2daad744cf0e6f99ebaff93a96c6bff2ae5e 100644 (file)
--- a/plat/socionext/uniphier/uniphier_bl2_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl2_setup.c
@@ -25,17 +25,21 @@
 #define UNIPHIER_IMAGE_BUF_SIZE                0x00100000UL
 
 static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE;
+static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
 static int uniphier_bl2_kick_scp;
 
 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
                                  u_register_t x2, u_register_t x3)
 {
-       uniphier_console_setup();
+       uniphier_soc = uniphier_get_soc_id();
+       if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
+               plat_error_handler(-ENOTSUP);
+
+       uniphier_console_setup(uniphier_soc);
 }
 
 void bl2_el3_plat_arch_setup(void)
 {
-       unsigned int soc;
        int skip_scp = 0;
        int ret;
 
@@ -45,19 +49,13 @@ void bl2_el3_plat_arch_setup(void)
        /* add relocation offset (run-time-address - link-address) */
        uniphier_mem_base += BL_CODE_BASE - BL2_BASE;
 
-       soc = uniphier_get_soc_id();
-       if (soc == UNIPHIER_SOC_UNKNOWN) {
-               ERROR("unsupported SoC\n");
-               plat_error_handler(-ENOTSUP);
-       }
-
-       ret = uniphier_io_setup(soc, uniphier_mem_base);
+       ret = uniphier_io_setup(uniphier_soc, uniphier_mem_base);
        if (ret) {
                ERROR("failed to setup io devices\n");
                plat_error_handler(ret);
        }
 
-       switch (uniphier_get_boot_master(soc)) {
+       switch (uniphier_get_boot_master(uniphier_soc)) {
        case UNIPHIER_BOOT_MASTER_THIS:
                INFO("Booting from this SoC\n");
                skip_scp = 1;

diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index 47f2378bcd5efd97477c500fe9c8f15a372f7a97..a25d6b751a145523eaf26766c3d6dc19d2635a6e 100644 (file)
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -21,6 +21,7 @@
 
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
+static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
 
 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
 {
@@ -37,7 +38,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
        bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
 
-       uniphier_console_setup();
+       uniphier_soc = uniphier_get_soc_id();
+       if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
+               plat_error_handler(-ENOTSUP);
+
+       uniphier_console_setup(uniphier_soc);
 
        while (bl_params) {
                if (bl_params->image_id == BL32_IMAGE_ID)
@@ -57,19 +62,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 void bl31_platform_setup(void)
 {
-       unsigned int soc;
-
-       soc = uniphier_get_soc_id();
-       if (soc == UNIPHIER_SOC_UNKNOWN) {
-               ERROR("unsupported SoC\n");
-               plat_error_handler(-ENOTSUP);
-       }
-
-       uniphier_cci_init(soc);
+       uniphier_cci_init(uniphier_soc);
        uniphier_cci_enable();
 
        /* Initialize the GIC driver, cpu and distributor interfaces */
-       uniphier_gic_driver_init(soc);
+       uniphier_gic_driver_init(uniphier_soc);
        uniphier_gic_init();
 
        /* Enable and initialize the System level generic timer */

diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c
index 64ee797148b976692f672de5554ec46886324032..1851e4da54a15c7dd7f986d8804ba109500ad395 100644 (file)
--- a/plat/socionext/uniphier/uniphier_console_setup.c
+++ b/plat/socionext/uniphier/uniphier_console_setup.c
@@ -1,9 +1,11 @@
 /*
- * Copyright (c) 2019, Socionext Inc. All rights reserved.
+ * Copyright (c) 2019-2020, Socionext Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <assert.h>
+
 #include <drivers/console.h>
 #include <errno.h>
 #include <lib/mmio.h>
@@ -12,9 +14,8 @@
 #include "uniphier.h"
 #include "uniphier_console.h"
 
-#define UNIPHIER_UART_BASE     0x54006800
-#define UNIPHIER_UART_END      0x54006c00
 #define UNIPHIER_UART_OFFSET   0x100
+#define UNIPHIER_UART_NR_PORTS 4
 
 struct uniphier_console {
        struct console console;
@@ -40,16 +41,26 @@ static struct uniphier_console uniphier_console = {
        },
 };
 
+static const uintptr_t uniphier_uart_base[] = {
+       [UNIPHIER_SOC_LD11] = 0x54006800,
+       [UNIPHIER_SOC_LD20] = 0x54006800,
+       [UNIPHIER_SOC_PXS3] = 0x54006800,
+};
+
 /*
  * There are 4 UART ports available on this platform. By default, we want to
  * use the same one as used in the previous firmware stage.
  */
-static uintptr_t uniphier_console_get_base(void)
+static uintptr_t uniphier_console_get_base(unsigned int soc)
 {
-       uintptr_t base = UNIPHIER_UART_BASE;
+       uintptr_t base, end;
        uint32_t div;
 
-       while (base < UNIPHIER_UART_END) {
+       assert(soc < ARRAY_SIZE(uniphier_uart_base));
+       base = uniphier_uart_base[soc];
+       end = base + UNIPHIER_UART_OFFSET * UNIPHIER_UART_NR_PORTS;
+
+       while (base < end) {
                div = mmio_read_32(base + UNIPHIER_UART_DLR);
                if (div)
                        return base;
@@ -66,11 +77,11 @@ static void uniphier_console_init(uintptr_t base)
                      UNIPHIER_UART_LCR_WLEN8 << 8);
 }
 
-void uniphier_console_setup(void)
+void uniphier_console_setup(unsigned int soc)
 {
        uintptr_t base;
 
-       base = uniphier_console_get_base();
+       base = uniphier_console_get_base(soc);
        if (!base)
                plat_error_handler(-EINVAL);