feat(nxp/common/errata): add SoC erratum a008850

Add SoC erratum a008850 support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1ef41c67737b7b5fdf1d892929a2d8040effc282

diff --git a/plat/nxp/common/soc_errata/errata.c b/plat/nxp/common/soc_errata/errata.c
index fb1818a85b5c384aba44823cb142e919f1b99b58..a117c916517d4c7a651f67a4fe5a2be935e5e930 100644 (file)
--- a/plat/nxp/common/soc_errata/errata.c
+++ b/plat/nxp/common/soc_errata/errata.c
@@ -14,6 +14,10 @@ void soc_errata(void)
 #ifdef ERRATA_SOC_A050426
        INFO("SoC workaround for Errata A050426 was applied\n");
        erratum_a050426();
+#endif
+#ifdef ERRATA_SOC_A008850
+       INFO("SoC workaround for Errata A008850 Early-Phase was applied\n");
+       erratum_a008850_early();
 #endif
        /*
         * The following DDR Erratas workaround are implemented in DDR driver,

diff --git a/plat/nxp/common/soc_errata/errata.h b/plat/nxp/common/soc_errata/errata.h
index b543b4bb968f1b80454c0ce7e0e1d43eee25e5cf..ab679957d4a3ebb1203a560ef351c5e74056079a 100644 (file)
--- a/plat/nxp/common/soc_errata/errata.h
+++ b/plat/nxp/common/soc_errata/errata.h
@@ -8,6 +8,8 @@
 #ifndef ERRATA_H
 #define ERRATA_H
 
+#include "errata_list.h"
+
 void soc_errata(void);
 
 #endif /* ERRATA_H */

diff --git a/plat/nxp/common/soc_errata/errata.mk b/plat/nxp/common/soc_errata/errata.mk
index 294261531f51001ceca66655cdc0aed98c832d3c..d2511bbb379182768823a963a1eaa4e7220be099 100644 (file)
--- a/plat/nxp/common/soc_errata/errata.mk
+++ b/plat/nxp/common/soc_errata/errata.mk
@@ -8,7 +8,8 @@
 # applied.
 
 ERRATA := \
-  ERRATA_SOC_A050426
+  ERRATA_SOC_A050426 \
+  ERRATA_SOC_A008850
 
 define enable_errata
   $(1) ?= 0

diff --git a/plat/nxp/common/soc_errata/errata_a008850.c b/plat/nxp/common/soc_errata/errata_a008850.c
new file mode 100644 (file)
index 0000000..e8c0f64
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata_a008850.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <cci.h>
+#include <common/debug.h>
+#include <ls_interconnect.h>
+#include <mmio.h>
+
+#include <platform_def.h>
+
+void erratum_a008850_early(void)
+{
+       /* part 1 of 2 */
+       uintptr_t cci_base = NXP_CCI_ADDR;
+       uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+       /* enabling forced barrier termination on CCI400 */
+       mmio_write_32(cci_base + CTRL_OVERRIDE_REG,
+                     (val | CCI_TERMINATE_BARRIER_TX));
+
+}
+
+void erratum_a008850_post(void)
+{
+       /* part 2 of 2 */
+       uintptr_t cci_base = NXP_CCI_ADDR;
+       uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+       /* Clear the BARRIER_TX bit */
+       val = val & ~(CCI_TERMINATE_BARRIER_TX);
+
+       /*
+        * Disable barrier termination on CCI400, allowing
+        * barriers to propagate across CCI
+        */
+       mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val);
+
+       INFO("SoC workaround for Errata A008850 Post-Phase was applied\n");
+}

diff --git a/plat/nxp/common/soc_errata/errata_list.h b/plat/nxp/common/soc_errata/errata_list.h
index 74d23150df4d18a1c884003c3597fae9dc01440f..ae95fa20313b304f5fae1f76fe7324af0e3d4055 100644 (file)
--- a/plat/nxp/common/soc_errata/errata_list.h
+++ b/plat/nxp/common/soc_errata/errata_list.h
@@ -12,4 +12,9 @@
 void erratum_a050426(void);
 #endif
 
+#ifdef ERRATA_SOC_A008850
+void erratum_a008850_early(void);
+void erratum_a008850_post(void);
+#endif
+
 #endif /* ERRATA_LIST_H */