Tegra: console clock settings for real/FPGA platforms

This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.

Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index b49665027165dfabb52e34cb3bbe6ed89786a071..9aacaa0584c316ad6b82c46fe06813feb458dff1 100644 (file)
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -27,6 +27,7 @@
 
 #include <memctrl.h>
 #include <tegra_def.h>
+#include <tegra_platform.h>
 #include <tegra_private.h>
 
 /* length of Trusty's input parameters (in bytes) */
@@ -122,6 +123,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
        plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
        image_info_t bl32_img_info = { {0} };
        uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
+       uint32_t console_clock;
 
        /*
         * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -164,6 +166,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
            (TEGRA_TZRAM_BASE != BL31_BASE))
                panic();
 
+       /*
+        * Reference clock used by the FPGAs is a lot slower.
+        */
+       if (tegra_platform_is_fpga() == 1U) {
+               console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+       } else {
+               console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+       }
+
        /*
         * Get the base address of the UART controller to be used for the
         * console
@@ -174,8 +185,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
                /*
                 * Configure the UART port to be used as the console
                 */
-               console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
-                       TEGRA_CONSOLE_BAUDRATE);
+               console_init(tegra_console_base, console_clock,
+                            TEGRA_CONSOLE_BAUDRATE);
        }
 
        /*

diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 8361ddd3d35602fcefadd3e07c78f67a75b464a8..ce44983b5f782da2083e03ea928fb2f7cb720bf4 100644 (file)
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -21,6 +21,7 @@
 #include <memctrl.h>
 #include <pmc.h>
 #include <tegra_def.h>
+#include <tegra_platform.h>
 #include <tegra_private.h>
 
 extern uint64_t tegra_bl31_phys_base;
@@ -222,6 +223,7 @@ __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
        plat_params_from_bl2_t *plat_params;
+       uint32_t console_clock;
 
        /*
         * Initialize the GIC cpu and distributor interfaces
@@ -234,10 +236,19 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
        if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
                        PSTATE_ID_SOC_POWERDN) {
 
+               /*
+                * Reference clock used by the FPGAs is a lot slower.
+                */
+               if (tegra_platform_is_fpga() == 1U) {
+                       console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+               } else {
+                       console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+               }
+
                /* Initialize the runtime console */
                if (tegra_console_base != (uint64_t)0) {
-                       console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
-                               TEGRA_CONSOLE_BAUDRATE);
+                       console_init(tegra_console_base, console_clock,
+                                    TEGRA_CONSOLE_BAUDRATE);
                }
 
                /*

diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index d10dc262aa91fa15066c3125c84a7c4f24f7d01c..0a0126b1e094d8232af8064fa8c55b5aa1b34177 100644 (file)
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -34,7 +34,8 @@
  * Platform console related constants
  ******************************************************************************/
 #define TEGRA_CONSOLE_BAUDRATE         U(115200)
-#define TEGRA_BOOT_UART_CLK_IN_HZ      U(408000000)
+#define TEGRA_BOOT_UART_CLK_13_MHZ     U(13000000)
+#define TEGRA_BOOT_UART_CLK_408_MHZ    U(408000000)
 
 /*******************************************************************************
  * Platform memory map related constants