Tegra: memctrl_v2: TZRAM aperture configuration settings

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.

Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index a03b6ef743122c2e55e014bc8de689c7110b742f..6f1d694756f1f7ca23abd39bafbdbbcfc05936e4 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -641,33 +641,55 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
  */
 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
-       uint64_t tzram_end = phys_base + size_in_bytes - 1;
+       uint32_t index;
+       uint32_t total_128kb_blocks = size_in_bytes >> 17;
+       uint32_t residual_4kb_blocks = (size_in_bytes & 0x1FFFF) >> 12;
        uint32_t val;
 
        /*
-        * Check if the TZRAM is locked already.
+        * Reset the access configuration registers to restrict access
+        * to the TZRAM aperture
         */
-       if (tegra_mc_read_32(MC_TZRAM_REG_CTRL) == DISABLE_TZRAM_ACCESS)
-               return;
+       for (index = MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0;
+            index <= MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5;
+            index += 4)
+               tegra_mc_write_32(index, 0);
 
        /*
-        * Setup the Memory controller to allow only secure accesses to
-        * the TZRAM carveout
+        * Allow CPU read/write access to the aperture
         */
-       INFO("Configuring TrustZone RAM (SysRAM) Memory Carveout\n");
+       tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1,
+               TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT |
+               TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT);
 
-       /* Program the base and end values */
-       tegra_mc_write_32(MC_TZRAM_BASE, (uint32_t)phys_base);
-       tegra_mc_write_32(MC_TZRAM_END, (uint32_t)tzram_end);
+       /*
+        * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
+        */
+       assert(!(phys_base & 0xFFF));
+       tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
+       tegra_mc_write_32(MC_TZRAM_BASE_HI,
+               (uint32_t)(phys_base >> 32) & TZRAM_BASE_HI_MASK);
 
-       /* Extract the high address bits from the base/end values */
-       val = (uint32_t)(phys_base >> 32) & TZRAM_ADDR_HI_BITS_MASK;
-       val |= (((uint32_t)(tzram_end >> 32) & TZRAM_ADDR_HI_BITS_MASK) <<
-               TZRAM_END_HI_BITS_SHIFT);
-       tegra_mc_write_32(MC_TZRAM_HI_ADDR_BITS, val);
+       /*
+        * Set the TZRAM size
+        *
+        * total size = (number of 128KB blocks) + (number of remaining 4KB
+        * blocks)
+        *
+        */
+       val = (residual_4kb_blocks << TZRAM_SIZE_RANGE_4KB_SHIFT) |
+             total_128kb_blocks;
+       tegra_mc_write_32(MC_TZRAM_SIZE, val);
 
-       /* Disable further writes to the TZRAM setup registers */
-       tegra_mc_write_32(MC_TZRAM_REG_CTRL, DISABLE_TZRAM_ACCESS);
+       /*
+        * Lock the configuration settings by disabling TZ-only lock
+        * and locking the configuration against any future changes
+        * at all.
+        */
+       val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
+       val &= ~TZRAM_ENABLE_TZ_LOCK_BIT;
+       val |= TZRAM_LOCK_CFG_SETTINGS_BIT;
+       tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
 
        /*
         * MCE propogates the security configuration values across the

diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index a7ab6503c137a236637121f1ca7af4fcd49fb3e8..e1abe14346eff3ded3bfcd1150d4119fc9adbeac 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -350,7 +350,7 @@ typedef struct mc_streamid_security_cfg {
                        .override_enable = OVERRIDE_ ## access \
                }
 
-#endif /* __ASSMEBLY__ */
+#endif /* __ASSEMBLY__ */
 
 /*******************************************************************************
  * TZDRAM carveout configuration registers
@@ -367,15 +367,35 @@ typedef struct mc_streamid_security_cfg {
 #define MC_VIDEO_PROTECT_SIZE_MB                       0x64c
 
 /*******************************************************************************
- * TZRAM carveout configuration registers
+ * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers
  ******************************************************************************/
-#define MC_TZRAM_BASE                                  0x1850
-#define MC_TZRAM_END                                   0x1854
-#define MC_TZRAM_HI_ADDR_BITS                          0x1588
- #define TZRAM_ADDR_HI_BITS_MASK                       0x3
- #define TZRAM_END_HI_BITS_SHIFT                       8
-#define MC_TZRAM_REG_CTRL                              0x185c
- #define DISABLE_TZRAM_ACCESS                          1
+#define MC_TZRAM_BASE_LO                               0x2194
+#define  TZRAM_BASE_LO_SHIFT                           12
+#define  TZRAM_BASE_LO_MASK                            0xFFFFF
+#define MC_TZRAM_BASE_HI                               0x2198
+#define  TZRAM_BASE_HI_SHIFT                           0
+#define  TZRAM_BASE_HI_MASK                            3
+#define MC_TZRAM_SIZE                                  0x219C
+#define  TZRAM_SIZE_RANGE_4KB_SHIFT                    27
+
+#define MC_TZRAM_CARVEOUT_CFG                          0x2190
+#define  TZRAM_LOCK_CFG_SETTINGS_BIT                   (1 << 1)
+#define  TZRAM_ENABLE_TZ_LOCK_BIT                      (1 << 0)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0           0x21A0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1           0x21A4
+#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT           (1 << 25)
+#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT            (1 << 7)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2           0x21A8
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3           0x21AC
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4           0x21B0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5           0x21B4
+
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0       0x21B8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1       0x21BC
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2       0x21C0
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3       0x21C4
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4       0x21C8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5       0x21CC
 
 /*******************************************************************************
  * Memory Controller Reset Control registers

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index f0bd5d57a75d4936c6d8b87f2114d76d6c5708dc..277b479e04bfdc78f028a266391e50f154232363 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -165,6 +165,6 @@
  * Tegra TZRAM constants
  ******************************************************************************/
 #define TEGRA_TZRAM_BASE               0x30000000
-#define TEGRA_TZRAM_SIZE               0x50000
+#define TEGRA_TZRAM_SIZE               0x40000
 
 #endif /* __TEGRA_DEF_H__ */