Tegra186: move TSA macros to tegra_def.h

This patch moves the TSA block's macros from memctrl_v2.h to
tegra_def.h in the Tegra186 tree.

Change-Id: I8b45dd3905c5d1f33ffb36d8b2de72aeb06674aa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 8b12dcd035c65154ba47882ef0b8588a8a3ba299..559ea2c59c1c933a9579e2060f7d3083e95a028a 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -392,43 +392,6 @@ typedef struct mc_streamid_security_cfg {
 #define  MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB                (1 << 24)
 #define MC_CLIENT_HOTRESET_STATUS1                     0x974
 
-/*******************************************************************************
- * TSA configuration registers
- ******************************************************************************/
-#define TSA_CONFIG_STATIC0_CSW_SESWR                   0x4010
-#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET            0x1100
-#define TSA_CONFIG_STATIC0_CSW_ETRW                    0x4038
-#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET             0x1100
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB                        0x5010
-#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET         0x1100
-#define TSA_CONFIG_STATIC0_CSW_AXISW                   0x7008
-#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET            0x1100
-#define TSA_CONFIG_STATIC0_CSW_HDAW                    0xA008
-#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET             0x100
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW                 0xB018
-#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET          0x1100
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW                 0xD018
-#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET          0x1100
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW                        0xD028
-#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET         0x1100
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW                 0x12018
-#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET          0x1100
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW                  0x13008
-#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET           0x1100
-#define TSA_CONFIG_STATIC0_CSW_AFIW                    0x13018
-#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET             0x1100
-#define TSA_CONFIG_STATIC0_CSW_SATAW                   0x13028
-#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET            0x1100
-#define TSA_CONFIG_STATIC0_CSW_EQOSW                   0x13038
-#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET            0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW               0x15008
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET                0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW              0x15018
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET       0x1100
-
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK           (0x3 << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU                (0 << 11)
-
 /*******************************************************************************
  * Memory Controller's PCFIFO client configuration registers
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 01da884f7b85913d963d78cec6a85c16f6b9f9ff..6bac0d7144b66f465ba233a47eb953c78e719cc5 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -114,6 +114,43 @@
  ******************************************************************************/
 #define TEGRA_TSA_BASE                 0x02400000
 
+/*******************************************************************************
+ * TSA configuration registers
+ ******************************************************************************/
+#define TSA_CONFIG_STATIC0_CSW_SESWR                   0x4010
+#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET            0x1100
+#define TSA_CONFIG_STATIC0_CSW_ETRW                    0x4038
+#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET             0x1100
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB                        0x5010
+#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET         0x1100
+#define TSA_CONFIG_STATIC0_CSW_AXISW                   0x7008
+#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET            0x1100
+#define TSA_CONFIG_STATIC0_CSW_HDAW                    0xA008
+#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET             0x100
+#define TSA_CONFIG_STATIC0_CSW_AONDMAW                 0xB018
+#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET          0x1100
+#define TSA_CONFIG_STATIC0_CSW_SCEDMAW                 0xD018
+#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET          0x1100
+#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW                        0xD028
+#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET         0x1100
+#define TSA_CONFIG_STATIC0_CSW_APEDMAW                 0x12018
+#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET          0x1100
+#define TSA_CONFIG_STATIC0_CSW_UFSHCW                  0x13008
+#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET           0x1100
+#define TSA_CONFIG_STATIC0_CSW_AFIW                    0x13018
+#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET             0x1100
+#define TSA_CONFIG_STATIC0_CSW_SATAW                   0x13028
+#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET            0x1100
+#define TSA_CONFIG_STATIC0_CSW_EQOSW                   0x13038
+#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET            0x1100
+#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW               0x15008
+#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET                0x1100
+#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW              0x15018
+#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET       0x1100
+
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK           (0x3 << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU                (0 << 11)
+
 /*******************************************************************************
  * Tegra Memory Controller constants
  ******************************************************************************/