Revert "riscv: Clear pending interrupts before enabling IPIs"

Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.

The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.

This reverts commit 7126b4ea19b65df7d4380fa58c54aa8c7ad3ef9c.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bf9fdf369b4473d02b541f0f296330cfcafaa942..e3222b1ea7c07a0ce50766a6965aa146e206229c 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,8 +65,6 @@ _start:
 #else
        li      t0, SIE_SSIE
 #endif
-       /* Clear any pending IPIs */
-       csrc    MODE_PREFIX(ip), t0
        csrs    MODE_PREFIX(ie), t0
 #endif