Tegra194: verify firewall settings before resource use

The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by other software components and so must be verified for correctness
before touching the hardware resources they protect.

This patch reads the firewall settings during early boot and asserts
if the settings mismatch.

Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index e39f9cad67b44ddcbc4a6240256041aa9f7d9016..6f44da619c30b3cbd7ae54260eb6ea7d5828108b 100644 (file)
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -294,4 +294,26 @@
 #define TEGRA_SID_XUSB_VF2                     U(0x5f)
 #define TEGRA_SID_XUSB_VF3                     U(0x60)
 
+/*******************************************************************************
+ * SCR addresses and expected settings
+ ******************************************************************************/
+#define SCRATCH_RSV68_SCR                      U(0x0C398110)
+#define SCRATCH_RSV68_SCR_VAL                  U(0x38000101)
+#define SCRATCH_RSV71_SCR                      U(0x0C39811C)
+#define SCRATCH_RSV71_SCR_VAL                  U(0x38000101)
+#define SCRATCH_RSV72_SCR                      U(0x0C398120)
+#define SCRATCH_RSV72_SCR_VAL                  U(0x38000101)
+#define SCRATCH_RSV75_SCR                      U(0x0C39812C)
+#define SCRATCH_RSV75_SCR_VAL                  U(0x3A000005)
+#define SCRATCH_RSV81_SCR                      U(0x0C398144)
+#define SCRATCH_RSV81_SCR_VAL                  U(0x3A000105)
+#define SCRATCH_RSV97_SCR                      U(0x0C398184)
+#define SCRATCH_RSV97_SCR_VAL                  U(0x38000101)
+#define SCRATCH_RSV99_SCR                      U(0x0C39818C)
+#define SCRATCH_RSV99_SCR_VAL                  U(0x38000101)
+#define SCRATCH_RSV109_SCR                     U(0x0C3981B4)
+#define SCRATCH_RSV109_SCR_VAL                 U(0x38000101)
+#define MISCREG_SCR_SCRTZWELCK                 U(0x00109000)
+#define MISCREG_SCR_SCRTZWELCK_VAL             U(0x30000100)
+
 #endif /* TEGRA_DEF_H */

diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index c0f2fb0177c88c31ef104c47cf5fa02da3e5f7a1..cb3d6b449f58c8dd28002fe8c7f0e09e62251332 100644 (file)
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -31,6 +31,27 @@
 /* ID for spe-console */
 #define TEGRA_CONSOLE_SPE_ID           0xFE
 
+/*******************************************************************************
+ * Structure to store the SCR addresses and its expected settings.
+ *******************************************************************************
+ */
+typedef struct {
+       uint32_t scr_addr;
+       uint32_t scr_val;
+} scr_settings_t;
+
+static const scr_settings_t t194_scr_settings[] = {
+       { SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL },
+       { SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL },
+       { SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL },
+       { SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL },
+       { SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL },
+       { SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL },
+       { SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL },
+       { SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL },
+       { MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL }
+};
+
 /*******************************************************************************
  * The Tegra power domain tree has a single system level power domain i.e. a
  * single root node. The first entry in the power domain descriptor specifies
@@ -196,6 +217,24 @@ void plat_enable_console(int32_t id)
 #endif
 }
 
+/*******************************************************************************
+ * Verify SCR settings
+ ******************************************************************************/
+static inline bool tegra194_is_scr_valid(void)
+{
+       uint32_t scr_val;
+       bool ret = true;
+
+       for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) {
+               scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr);
+               if (scr_val != t194_scr_settings[i].scr_val) {
+                       ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr);
+                       ret = false;
+               }
+       }
+       return ret;
+}
+
 /*******************************************************************************
  * Handler for early platform setup
  ******************************************************************************/
@@ -208,6 +247,11 @@ void plat_early_platform_setup(void)
        /* Verify chip id is t194 */
        assert(tegra_chipid_is_t194());
 
+       /* Verify SCR settings */
+       if (tegra_platform_is_silicon()) {
+               assert(tegra194_is_scr_valid());
+       }
+
        /* sanity check MCE firmware compatibility */
        mce_verify_firmware_version();