fix(el3_runtime): allow SErrors when executing in EL3

SCR_EL3.EA is set to 1 in BL31 initialization and is cleared before
entering to lower ELs(except for RAS FFH case "HANDLE_EA_EL3_FIRST_NS").
The cleared value persist even during run time when execution comes
back to EL3.

When SCR_EL3.EA is 0 and execution state is EL3, Async EAs(delivered
as SErrors) are implicitly masked and hence any Async EA by EL3 will
remain pending and will trap at the exception level EA is targeted
to and unmasked when entering lower EL.
This causes unexpected EA at lower EL. This is a very rare
to get SError in EL3 until unless there is any programming error.

This patch sets SCR_EL3.EA to 1 when entering EL3 from lower EL.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibb593369edb034f670fd85ee79adc9829b900a83

diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index b126b9cd82502529c841670d003ba482a6e34e31..60501f615bfaed6ca81b32d1fb6dc563dcc9a7ef 100644 (file)
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -787,6 +787,15 @@ func fpregs_context_restore
 endfunc fpregs_context_restore
 #endif /* CTX_INCLUDE_FPREGS */
 
+       /*
+        * Set SCR_EL3.EA bit to enable SErrors at EL3
+        */
+       .macro enable_serror_at_el3
+       mrs     x8, scr_el3
+       orr     x8, x8, #SCR_EA_BIT
+       msr     scr_el3, x8
+       .endm
+
        /*
         * Set the PSTATE bits not set when the exception was taken as
         * described in the AArch64.TakeException() pseudocode function
@@ -917,6 +926,7 @@ endfunc fpregs_context_restore
  */
 func prepare_el3_entry
        save_gp_pmcr_pauth_regs
+       enable_serror_at_el3
        /*
         * Set the PSTATE bits not described in the Aarch64.TakeException
         * pseudocode to their default values.