#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "osc25";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/*** primary clock domains ***/
clock-names = "ref";
reg = <0x1F04D020 0x0008>;
clock-output-names = "ethpll";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/******** clocks ********/
clock-div = <10>;
clock-mult = <1>;
clock-output-names = "div125m";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
div_156m:div_156m {
reg = <0x1F04D084 0x0004>;
clock-output-names = "baudclk";
divider-width = <9>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
wdt_clk:wdt_clk@1F04D150 {
clock-div = <1>;
clock-mult = <1>;
clock-output-names = "i2cclk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/** eth_pll -> div_156m domain **/