Tegra: allow individual SoCs to restore their settings

This patch uses the Memory controller driver's handler to restore
its settings and moves the other chip specific code to their own
'pwr_domain_on_finish' handlers.

Change-Id: I3c9d23bdab9e2e3c05034ff6812cf941ccd7a75e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index 0003446f9cc0c2fc2c7f949d71eb0bbd7db6c981..c4170504c43801bbd2985fa053ff2fa9e267d9f2 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -89,6 +89,14 @@ void tegra_memctrl_setup(void)
        tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
 }
 
+/*
+ * Restore Memory Controller settings after "System Suspend"
+ */
+void tegra_memctrl_restore_settings(void)
+{
+       tegra_memctrl_setup();
+}
+
 /*
  * Secure the BL31 DRAM aperture.
  *

diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 683af2814eb36ffd2a92d9b636d3e779d2befe9f..64405fb3a0ce8d5755652e4c0ad9ee4cf774b928 100644 (file)
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -168,14 +168,10 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
                        PSTATE_ID_SOC_POWERDN) {
 
                /*
-                * Lock scratch registers which hold the CPU vectors.
+                * Restore Memory Controller settings as it loses state
+                * during system suspend.
                 */
-               tegra_pmc_lock_cpu_vectors();
-
-               /*
-                * SMMU configuration.
-                */
-               tegra_memctrl_setup();
+               tegra_memctrl_restore_settings();
 
                /*
                 * Security configuration to allow DRAM/device access.

diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h
index db98fc074ae7e983439580f94afb94e8d9d6e5dd..a3f08755acf8c5bbd87a48547b3ebd5e6e1c1d19 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl.h
@@ -32,6 +32,7 @@
 #define __MEMCTRL_H__
 
 void tegra_memctrl_setup(void);
+void tegra_memctrl_restore_settings(void);
 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);

diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
index 2abb2929fdcbb04dfd8f0780ee534c5d231f6da3..f05f3d0e9f85c5f1cef3fd646d13990bcc19253c 100644 (file)
--- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
@@ -107,6 +107,16 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
        return PSCI_E_SUCCESS;
 }
 
+int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+       /*
+        * Lock scratch registers which hold the CPU vectors
+        */
+       tegra_pmc_lock_cpu_vectors();
+
+       return PSCI_E_SUCCESS;
+}
+
 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 {
        tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);

diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index 332de2567a9d699cd29546c3c592497727b80140..95fb93fe00efa991e37ecc5289e9e52885550a36 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -154,6 +154,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
        if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
                        PLAT_SYS_SUSPEND_STATE_ID) {
 
+               /*
+                * Lock scratch registers which hold the CPU vectors
+                */
+               tegra_pmc_lock_cpu_vectors();
+
                /*
                 * Enable WRAP to INCR burst type conversions for
                 * incoming requests on the AXI slave ports.