fix(layerscape): unlock write access SMMU_CBn_ACTLR

This patch is to fix Errata #841119 and #826419 failed apply in linux
because of SMMU_CBn_ACTLR register can't be modified in non-secure
states.

Signed-off-by: Howard Lu <howard.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2b23e7c8baa809f385917eb45b10ec6b26a9ada8

diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h
index d64c33b2064e1ead00a524ebdd21f713e9630970..bc17703dc8b1b412aecb6ac29e6ad2722f7604ab 100644 (file)
--- a/include/drivers/nxp/smmu/nxp_smmu.h
+++ b/include/drivers/nxp/smmu/nxp_smmu.h
@@ -10,10 +10,13 @@
 
 #define SMMU_SCR0              (0x0)
 #define SMMU_NSCR0             (0x400)
+#define SMMU_SACR              (0x10)
 
 #define SCR0_CLIENTPD_MASK     0x00000001
 #define SCR0_USFCFG_MASK       0x00000400
 
+#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT      (1ULL << 26U)
+
 static inline void bypass_smmu(uintptr_t smmu_base_addr)
 {
        uint32_t val;
@@ -27,4 +30,13 @@ static inline void bypass_smmu(uintptr_t smmu_base_addr)
        mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
 }
 
+static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
+{
+       uint32_t val;
+
+       val = mmio_read_32((smmu_base_addr + SMMU_SACR));
+       val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
+       mmio_write_32((smmu_base_addr + SMMU_SACR), val);
+}
+
 #endif

diff --git a/plat/nxp/soc-ls1043a/soc.c b/plat/nxp/soc-ls1043a/soc.c
index 7badf8c386cb05571b2ae4a6fc2999530420379f..3e821d0c2ba7d9ae28e691412505dee39aa722d0 100644 (file)
--- a/plat/nxp/soc-ls1043a/soc.c
+++ b/plat/nxp/soc-ls1043a/soc.c
@@ -21,9 +21,7 @@
 #ifdef POLICY_FUSE_PROVISION
 #include <nxp_gpio.h>
 #endif
-#if TRUSTED_BOARD_BOOT
 #include <nxp_smmu.h>
-#endif
 #include <nxp_timer.h>
 #include <plat_console.h>
 #include <plat_gic.h>
@@ -174,6 +172,12 @@ void soc_early_init(void)
        get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
        plat_ls_interconnect_enter_coherency(num_clusters);
 
+       /*
+        * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+        */
+       smmu_cache_unlock(NXP_SMMU_ADDR);
+       INFO("SMMU Cache Unlocking is Configured.\n");
+
 #if TRUSTED_BOARD_BOOT
        uint32_t mode;
 

diff --git a/plat/nxp/soc-ls1043a/soc.mk b/plat/nxp/soc-ls1043a/soc.mk
index b6ce14e5ee144a222ae7351c9972f763ea63a6a3..0ebb3774d09ebe486c0adec195c9d8d5bf77447b 100644 (file)
--- a/plat/nxp/soc-ls1043a/soc.mk
+++ b/plat/nxp/soc-ls1043a/soc.mk
@@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
 
 # For Security Features
 DISABLE_FUSE_WRITE     := 1
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
 $(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
 $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
 $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
 SECURE_BOOT    := yes

diff --git a/plat/nxp/soc-ls1046a/soc.c b/plat/nxp/soc-ls1046a/soc.c
index d17e67219f56a7160721b9d4de036f24f5efd1e6..6dfea89bbbc1abdf681f7a5d58cb20f6432d0aa2 100644 (file)
--- a/plat/nxp/soc-ls1046a/soc.c
+++ b/plat/nxp/soc-ls1046a/soc.c
@@ -21,9 +21,7 @@
 #ifdef POLICY_FUSE_PROVISION
 #include <nxp_gpio.h>
 #endif
-#if TRUSTED_BOARD_BOOT
 #include <nxp_smmu.h>
-#endif
 #include <nxp_timer.h>
 #include <plat_console.h>
 #include <plat_gic.h>
@@ -168,6 +166,12 @@ void soc_early_init(void)
        get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
        plat_ls_interconnect_enter_coherency(num_clusters);
 
+       /*
+        * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+        */
+       smmu_cache_unlock(NXP_SMMU_ADDR);
+       INFO("SMMU Cache Unlocking is Configured.\n");
+
 #if TRUSTED_BOARD_BOOT
        uint32_t mode;
 

diff --git a/plat/nxp/soc-ls1046a/soc.mk b/plat/nxp/soc-ls1046a/soc.mk
index 8207dcd80861695ee5791e6ca39451e50a883405..76440271921bfebb132bae55f5c7e92bae28ac13 100644 (file)
--- a/plat/nxp/soc-ls1046a/soc.mk
+++ b/plat/nxp/soc-ls1046a/soc.mk
@@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
 
 # For Security Features
 DISABLE_FUSE_WRITE     := 1
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
 $(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
 $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
 $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
 SECURE_BOOT    := yes

diff --git a/plat/nxp/soc-ls1088a/soc.c b/plat/nxp/soc-ls1088a/soc.c
index 5f9f313e2dc25d39483b0c1a66050800b1f8d1a7..02d62ea8889babfe865ca7548519173df62e30f9 100644 (file)
--- a/plat/nxp/soc-ls1088a/soc.c
+++ b/plat/nxp/soc-ls1088a/soc.c
@@ -17,9 +17,7 @@
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <ls_interconnect.h>
-#if TRUSTED_BOARD_BOOT
 #include <nxp_smmu.h>
-#endif
 #include <nxp_timer.h>
 #include <plat_console.h>
 #include <plat_gic.h>
@@ -254,6 +252,12 @@ void soc_early_init(void)
                                MT_DEVICE | MT_RW | MT_NS);
        }
 
+       /*
+        * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+        */
+       smmu_cache_unlock(NXP_SMMU_ADDR);
+       INFO("SMMU Cache Unlocking is Configured.\n");
+
 #if TRUSTED_BOARD_BOOT
        uint32_t mode;
 

diff --git a/plat/nxp/soc-ls1088a/soc.mk b/plat/nxp/soc-ls1088a/soc.mk
index 83ac9d08f1cf208cba7dc9f43329ac706b9ab430..6e39461e3dc4c2540cf4de9d02848796cabe6561 100644 (file)
--- a/plat/nxp/soc-ls1088a/soc.mk
+++ b/plat/nxp/soc-ls1088a/soc.mk
@@ -23,12 +23,12 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
 
 # For Security Features
 DISABLE_FUSE_WRITE     := 1
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
 ifeq (${TRUSTED_BOARD_BOOT}, 1)
 ifeq (${GENERATE_COT},1)
 # Save Keys to be used by DDR FIP image
 SAVE_KEYS=1
 endif
-$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
 $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
 $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
 # Used by create_pbl tool to

diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c
index df313935ce608eee267298576f8feb6ee3c8c034..427189dc5d7f8df5effd93a4b7876421845be7ab 100644 (file)
--- a/plat/nxp/soc-lx2160a/soc.c
+++ b/plat/nxp/soc-lx2160a/soc.c
@@ -23,9 +23,7 @@
 #ifdef POLICY_FUSE_PROVISION
 #include <nxp_gpio.h>
 #endif
-#if TRUSTED_BOARD_BOOT
 #include <nxp_smmu.h>
-#endif
 #include <nxp_timer.h>
 #include <plat_console.h>
 #include <plat_gic.h>
@@ -286,6 +284,12 @@ void soc_early_init(void)
        sfp_init(NXP_SFP_ADDR);
 #endif
 
+       /*
+        * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+        */
+       smmu_cache_unlock(NXP_SMMU_ADDR);
+       INFO("SMMU Cache Unlocking is Configured.\n");
+
 #if TRUSTED_BOARD_BOOT
        uint32_t mode;
 

diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
index 75a3af29499d4009ab588b45dacb29008a4a6668..239442c20c4fc111d90fc9fdfe8551f040c74f1f 100644 (file)
--- a/plat/nxp/soc-lx2160a/soc.mk
+++ b/plat/nxp/soc-lx2160a/soc.mk
@@ -36,12 +36,12 @@ endif
 
  # For Security Features
 DISABLE_FUSE_WRITE     := 1
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
 ifeq (${TRUSTED_BOARD_BOOT}, 1)
 ifeq (${GENERATE_COT},1)
 # Save Keys to be used by DDR FIP image
 SAVE_KEYS=1
 endif
-$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
 $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
 $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
 # Used by create_pbl tool to