plat: marvell: armada: a8k: change CCU LLC SRAM mapping

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index bec0bcbd4ce03ad5c5e333f18cbb133e802f1331..da4ba565a7242d4d4fe6b2ac38c96c810187d4c4 100644 (file)
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -79,10 +79,12 @@ There are several build options:
 
 - LLC_SRAM
 
-        Flag defining the LLC (L3) cache SRAM support. The feature is
-        disabled by default (``LLC_ENABLE=0``).
-        When LLC SRAM is enabled, the secure payload (BL32) is loaded into this
-        SRAM area instead of the DRAM.
+        Flag enabling the LLC (L3) cache SRAM support. The LLC SRAM is activated and used
+        by Trusted OS (OP-TEE OS, BL32). The TF-A only prepares CCU address translation windows
+        for SRAM address range at BL31 execution stage with window target set to DRAM-0.
+        When Trusted OS activates LLC SRAM, the CCU window target is changed to SRAM.
+        There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
+        Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
 
 - MARVELL_SECURE_BOOT
 

diff --git a/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
index 7d30ebe5a70332657e4639f2015d80b56440bdf4..a4092610292ae13414b87e5e4f62470e1ff22a88 100644 (file)
--- a/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c
@@ -103,7 +103,10 @@ struct addr_map_win ccu_memory_map[] = {   /* IO window */
        {0x00000000f2000000,    0x4000000,      IO_0_TID}, /* IO window */
 #else
 #if LLC_SRAM
-       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+       /* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+        * and changes the window target to SRAM_TID.
+        */
+       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
 #endif
        {0x00000000f2000000,    0xe000000,      IO_0_TID},
        {0x00000000c0000000,    0x30000000,     IO_0_TID}, /* IO window */

diff --git a/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
index 7fc33f1f908a6ff467f3ab4bb6af76330e2745f6..3b68e91ba014b6eaa4d0e24ce71638b05c148ef0 100644 (file)
--- a/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c
@@ -94,7 +94,10 @@ struct addr_map_win ccu_memory_map[] = {
        {0x00000000f2000000,    0x4000000,      IO_0_TID}, /* IO window */
 #else
 #if LLC_SRAM
-       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+       /* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+        * and changes the window target to SRAM_TID.
+        */
+       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
 #endif
        {0x00000000f2000000,    0xe000000,      IO_0_TID},
        {0x00000000c0000000,    0x30000000,     IO_0_TID}, /* IO window */

diff --git a/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
index 856c07a6e320eeeaa30d14b6224a309edb9eee02..4ccda14e95c788edaa284ed09f2c948ac90ab2d6 100644 (file)
--- a/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c
@@ -132,7 +132,10 @@ struct addr_map_win ccu_memory_map[] = {
        {0x00000000f2000000,    0x4000000,  IO_0_TID}, /* IO window */
 #else
 #if LLC_SRAM
-       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+       /* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+        * and changes the window target to SRAM_TID.
+        */
+       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
 #endif
        {0x00000000f2000000,    0xe000000,  IO_0_TID}, /* IO window */
        {0x00000000c0000000,    0x30000000,  IO_0_TID}, /* IO window */

diff --git a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
index 0edc977458f34e393ba9c38b2caf077f85b2ea55..b9329675f0431459bbed6dea17a82cfe77c9ca59 100644 (file)
--- a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c
@@ -166,7 +166,10 @@ struct addr_map_win ccu_memory_map[] = {
        {0x00000000f2000000,    0x4000000,  IO_0_TID}, /* IO window */
 #else
 #if LLC_SRAM
-       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID},
+       /* This entry is prepared for OP-TEE OS that enables the LLC SRAM
+        * and changes the window target to SRAM_TID.
+        */
+       {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
 #endif
        {0x00000000f2000000,    0xe000000,  IO_0_TID}, /* IO window */
        {0x00000000c0000000,    0x30000000,  IO_0_TID}, /* IO window */

diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index cbef3a173c8d861736f42b672b2fcdd1f5ae5de0..944a1517ba5ffebfd4b7e3e09db185b60cbb9172 100644 (file)
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -96,13 +96,13 @@
 #define PLAT_MARVELL_TRUSTED_ROM_BASE          PLAT_MARVELL_ATF_LOAD_ADDR
 /* 4 MB for FIP image */
 #define PLAT_MARVELL_TRUSTED_ROM_SIZE          0x00400000
-/* Reserve 12M for SCP (Secure PayLoad) Trusted RAM
- * OP-TEE SHMEM follows this region
+/* Reserve 12MB for SCP (Secure PayLoad) Trusted RAM
+ * OP-TEE 4MB SHMEM follows this region
  */
 #define PLAT_MARVELL_TRUSTED_RAM_BASE          0x04400000
 #define PLAT_MARVELL_TRUSTED_RAM_SIZE          0x00C00000      /* 12 MB DRAM */
 
-#define PLAT_MARVELL_LLC_SRAM_BASE             PLAT_MARVELL_TRUSTED_RAM_BASE
+#define PLAT_MARVELL_LLC_SRAM_BASE             0x05400000
 #define PLAT_MARVELL_LLC_SRAM_SIZE             0x00100000      /* 1 MB SRAM */
 
 /*

diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index fcc97acd3670ec2af0f53fae8f23560eac4c0d1c..5c8c7db2d751aa58793342ce8205beb149179a46 100644 (file)
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -22,15 +22,7 @@ LLC_SRAM                     := 0
 $(eval $(call add_define,LLC_SRAM))
 
 # Enable/Disable LLC
-ifeq (${LLC_SRAM}, 0)
 LLC_ENABLE                     := 1
-else
-# When LLC_SRAM=1, the entire LLC converted to SRAM and enabled at BL1.
-# All existing cases activating LLC at BL31 stage should be disabled.
-# The below assignment does not allow changing the LLC_ENABLE
-# value in the command line.
-LLC_ENABLE                     = 0
-endif
 $(eval $(call add_define,LLC_ENABLE))
 
 include lib/xlat_tables_v2/xlat_tables.mk