drm/msm/dpu: fix len of sc7180 ctl blocks

[ Upstream commit 855380e317c29c094c169f2f0d168a01ce04fb51 ]

Change sc7180's ctl block len to 0x1dc.

Fixes: f011559e2263 ("msm:disp:dpu1: add support for display for SC7180 target")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/522210/
Link: https://lore.kernel.org/r/20230211231259.1308718-5-dmitry.baryshkov@linaro.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index e3f1661b846095659db396ea51288a94f544f04b..48fedd3f182e680091b88b876933af1e5e7eefc7 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -607,19 +607,19 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
 static const struct dpu_ctl_cfg sc7180_ctl[] = {
        {
        .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0xE4,
+       .base = 0x1000, .len = 0x1dc,
        .features = BIT(DPU_CTL_ACTIVE_CFG),
        .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        },
        {
        .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0xE4,
+       .base = 0x1200, .len = 0x1dc,
        .features = BIT(DPU_CTL_ACTIVE_CFG),
        .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        },
        {
        .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0xE4,
+       .base = 0x1400, .len = 0x1dc,
        .features = BIT(DPU_CTL_ACTIVE_CFG),
        .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
        },