mediatek: mt8192: Fix non-MISRA compliant code

CID 364144: Integer handling issues (NO_EFFECT)

The unsigned value is always greater-than-or-equal-to-zero.
Remove such check.

Change-Id: Ia395eb32f55a7098d2581ce7f548b7e1112beaa0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>

diff --git a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c
index 053d21081bac36536b4785b6fcc805a6b01c2ad7..f1d84938636b22cf100474754fa57c92fb9b355b 100644 (file)
--- a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c
+++ b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c
@@ -39,15 +39,15 @@ void ptp3_init(unsigned int core)
 {
        unsigned int _core;
 
-       if (core >= PTP3_CFG1_CPU_START_ID) {
-               if (core < NR_PTP3_CFG1_CPU) {
-                       /* update ptp3_cfg1 */
-                       ptp3_write(
-                               ptp3_cfg1[core][PTP3_CFG_ADDR],
-                               ptp3_cfg1[core][PTP3_CFG_VALUE]);
-               }
+       /* Apply ptp3_cfg1 for core 0 to 7 */
+       if (core < NR_PTP3_CFG1_CPU) {
+               /* update ptp3_cfg1 */
+               ptp3_write(
+                       ptp3_cfg1[core][PTP3_CFG_ADDR],
+                       ptp3_cfg1[core][PTP3_CFG_VALUE]);
        }
 
+       /* Apply ptp3_cfg2 for core 4 to 7 */
        if (core >= PTP3_CFG2_CPU_START_ID) {
                _core = core - PTP3_CFG2_CPU_START_ID;
 
@@ -59,6 +59,7 @@ void ptp3_init(unsigned int core)
                }
        }
 
+       /* Apply ptp3_cfg3 for core 4 to 7 */
        if (core >= PTP3_CFG3_CPU_START_ID) {
                _core = core - PTP3_CFG3_CPU_START_ID;
 
@@ -73,13 +74,11 @@ void ptp3_init(unsigned int core)
 
 void ptp3_deinit(unsigned int core)
 {
-       if (core >= PTP3_CFG1_CPU_START_ID) {
-               if (core < NR_PTP3_CFG1_CPU) {
-                       /* update ptp3_cfg1 */
-                       ptp3_write(
-                               ptp3_cfg1[core][PTP3_CFG_ADDR],
-                               ptp3_cfg1[core][PTP3_CFG_VALUE] &
-                                        ~PTP3_CFG1_MASK);
-               }
+       if (core < NR_PTP3_CFG1_CPU) {
+               /* update ptp3_cfg1 */
+               ptp3_write(
+                       ptp3_cfg1[core][PTP3_CFG_ADDR],
+                       ptp3_cfg1[core][PTP3_CFG_VALUE] &
+                                ~PTP3_CFG1_MASK);
        }
 }