Tegra210: deassert CPU reset signals during power on

This patch de-asserts the CPU reset signals for each CPU as
part of it's power on sequence. This is needed to get rid of
the wait in BPMP firmware during SC7 exit.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index f594d2097263af19ec963ea3c65a7efff57f66bc..010899ac34b4b5010278427a42add454f7fbe291 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -40,6 +40,13 @@
 #include <tegra_def.h>
 #include <tegra_private.h>
 
+/*
+ * Register used to clear CPU reset signals. Each CPU has two reset
+ * signals: CPU reset (3:0) and Core reset (19:16).
+ */
+#define CPU_CMPLX_RESET_CLR            0x454
+#define CPU_CORE_RESET_MASK            0x10001
+
 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
 
 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
@@ -116,6 +123,10 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr)
 int tegra_prepare_cpu_on(unsigned long mpidr)
 {
        int cpu = mpidr & MPIDR_CPU_MASK;
+       uint32_t mask = CPU_CORE_RESET_MASK << cpu;
+
+       /* Deassert CPU reset signals */
+       mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
 
        /* Turn on CPU using flow controller or PMC */
        if (cpu_powergate_mask[cpu] == 0) {