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Add note about erratum 814220 for A7
authorJoel Hutton <Joel.Hutton@Arm.com>
Tue, 9 Apr 2019 13:45:34 +0000 (14:45 +0100)
committerJoel Hutton <Joel.Hutton@arm.com>
Wed, 10 Apr 2019 09:57:58 +0000 (10:57 +0100)
commitf999faca06e8ff5d6d23a08d844c6a4ad38e3000
tree0a4bdd798e26ca9e54018ce623252bb611ce6536tree | snapshot
parenta738e1554c2daf7511af3543addd07c956268d14commit | diff
Add note about erratum 814220 for A7

On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.

Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
lib/aarch32/cache_helpers.S diff | blob | history
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