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(parent: bc1ed6a) | patch
arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills
authorFlorian Fainelli <f.fainelli@gmail.com>
Thu, 20 Apr 2017 19:05:45 +0000 (12:05 -0700)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 28 Apr 2017 14:23:36 +0000 (15:23 +0100)
commitf8ff7942f1453db1b1eb563fd0e1d2ed5fbff104
tree44a7b3559a6c24f2f7e4dbe731251b0b652e3131tree | snapshot
parentbc1ed6a25e05056b74e9c21b107a32fa97213cd5commit | diff
arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills

Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/perf_event.c diff | blob | history
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