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(parent: 61e18e9) | patch
drm/fsl-dcu: specify volatile registers
authorStefan Agner <stefan@agner.ch>
Wed, 18 Nov 2015 02:05:25 +0000 (18:05 -0800)
committerStefan Agner <stefan@agner.ch>
Fri, 26 Feb 2016 00:13:16 +0000 (16:13 -0800)
commitf89e5ff3b86d0674035fe33da5b6bf5e46206676
tree279c06460c0b24a8edefc58aa34ac609f5721a66tree | snapshot
parent61e18e9292e5057c715603de433a5b490fea7ac0commit | diff
drm/fsl-dcu: specify volatile registers

Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.

Signed-off-by: Stefan Agner <stefan@agner.ch>
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c diff | blob | history
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