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(parent: 8a1fdb8) | patch
drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b
authorJani Nikula <jani.nikula@intel.com>
Thu, 9 Sep 2021 12:52:04 +0000 (15:52 +0300)
committerJani Nikula <jani.nikula@intel.com>
Mon, 20 Sep 2021 15:47:00 +0000 (18:47 +0300)
commitf6222f90bfccd3ea0bd64f86f8b7606b193aa34a
tree9ee70c7e8cce7eba953be67ae0d582577b8467d6tree | snapshot
parent8a1fdb895330e2a932f3915bd343cbcf3ad1fac8commit | diff
drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b

There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.

v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper

Bspec: 54128
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_dp_mst.c diff | blob | history
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