]> git.baikalelectronics.ru Git - kernel.git/commit
net: axienet: increase default TX ring size to 128
authorRobert Hancock <robert.hancock@calian.com>
Tue, 18 Jan 2022 21:41:32 +0000 (15:41 -0600)
committerDavid S. Miller <davem@davemloft.net>
Wed, 19 Jan 2022 11:29:14 +0000 (11:29 +0000)
commitf4d864d6a0f920398fca26509c2b416bdbdb6ca2
tree5e43d89d4f58a4f78e4feaca881789e8c8ea0be6
parent958678cc595eb0cb969a4c033b62579a7fce6050
net: axienet: increase default TX ring size to 128

With previous changes to make the driver handle the TX ring size more
correctly, the default TX ring size of 64 appears to significantly
bottleneck TX performance to around 600 Mbps on a 1 Gbps link on ZynqMP.
Increasing this to 128 seems to bring performance up to near line rate and
shouldn't cause excess bufferbloat (this driver doesn't yet support modern
byte-based queue management).

Fixes: e69e5783903ef ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/xilinx/xilinx_axienet_main.c