]> git.baikalelectronics.ru Git - arm-tf.git/commit
Prevent speculative execution past ERET
authorAnthony Steinhauser <asteinhauser@google.com>
Tue, 7 Jan 2020 23:44:06 +0000 (15:44 -0800)
committerAnthony Steinhauser <asteinhauser@google.com>
Wed, 22 Jan 2020 21:42:51 +0000 (21:42 +0000)
commitf461fe346b728d0e88142fd7b8f2816415af18bc
tree580fd936db8a2345ee90982b4c3fb813e566dbe3
parentd81e38f66e232ddd2590f50cafe88eef52d4a752
Prevent speculative execution past ERET

Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).

This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8
https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61
https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2
https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a

It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c

Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
bl1/aarch64/bl1_exceptions.S
bl2/aarch64/bl2_el3_entrypoint.S
bl31/aarch64/runtime_exceptions.S
bl32/tsp/aarch64/tsp_exceptions.S
include/arch/aarch64/asm_macros.S
lib/cpus/aarch64/cortex_a76.S
lib/cpus/aarch64/neoverse_n1.S
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
lib/el3_runtime/aarch64/context.S
plat/renesas/rcar/aarch64/plat_helpers.S
services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S