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(parent: e180f3a) | patch
armv8/cache.S: Triple with single instruction
authorPierre-Clément Tosi <ptosi@google.com>
Fri, 27 Aug 2021 16:04:10 +0000 (18:04 +0200)
committerTom Rini <trini@konsulko.com>
Thu, 23 Sep 2021 12:55:06 +0000 (08:55 -0400)
commitf333361abee39199b45b357be589ea649adddb6c
tree6fcc08d95f57b7523b77b701e892a6e2ec86b12ftree | snapshot
parente180f3aa00b482ba296c74765849b650377e89f8commit | diff
armv8/cache.S: Triple with single instruction

Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.

Fix the comment as the tripled cache level is placed in x12, not x0.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
arch/arm/cpu/armv8/cache.S diff | blob | history
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