riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>