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(parent: ba8fdbe) | patch
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
authorGabriel Fernandez <gabriel.fernandez@st.com>
Thu, 16 Mar 2017 08:16:40 +0000 (09:16 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 4 Apr 2017 00:57:54 +0000 (17:57 -0700)
commitee922efa4d4967a25177f233ce59c7ad8ac00738
tree68ba0638bbf1ee1f4c30460044db8e6f51d22103tree | snapshot
parentba8fdbee73eb446741a3c4b966b4b2adaebfcd76commit | diff
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ

0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
...
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 1

Use divider table to exclude 0 and 1 values.

Fixes: 3741d202442f ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-stm32f4.c diff | blob | history
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