]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Fix fastset vs. pfit on/off on HSW EDP transcoder
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 25 Apr 2019 16:29:05 +0000 (19:29 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 9 May 2019 13:01:22 +0000 (16:01 +0300)
commite83d302d3e7815584cfdf939c03cb9cf234da0d7
treeb5d2b7b4ff59fd569566833fecb7dfedbafffcad
parent7d8b184349051cefa6648eb1ca2c3b9de6f6535a
drm/i915: Fix fastset vs. pfit on/off on HSW EDP transcoder

On HSW the pipe A panel fitter lives inside the display power well,
and the input MUX for the EDP transcoder needs to be configured
appropriately to route the data through the power well as needed.
Changing the MUX setting is not allowed while the pipe is active,
so we need to force a full modeset whenever we need to change it.

Currently we may end up doing a fastset which won't change the
MUX settings, but it will drop the power well reference, and that
kills the pipe.

Cc: stable@vger.kernel.org
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fixes: 34baad1279a9 ("drm/i915: Enable fastset for non-boot modesets.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190425162906.5242-1-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_pipe_crc.c