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ARM: dts: dra7: fix cpsw mdio fck clock
authorGrygorii Strashko <grygorii.strashko@ti.com>
Mon, 18 Nov 2019 12:20:16 +0000 (14:20 +0200)
committerTony Lindgren <tony@atomide.com>
Wed, 20 Nov 2019 17:42:33 +0000 (09:42 -0800)
commite4be154983d8e1b20a112a572696bee516ce2dc9
tree6d6f56161a8d6bc9cd08cbbbbc8e0328d2864ab1tree | snapshot
parentd51e64b58c1147451a1948a9613d1661a9be3016commit | diff
ARM: dts: dra7: fix cpsw mdio fck clock

The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)
is specified incorrectly, which is caused incorrect MDIO bus clock
configuration MDCLK. The correct CPSW MDIO functional clock is
gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.

Fixes: f7a7eb3d04ab ("ARM: dts: Add fck for cpsw mdio for omap variants")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dra7-l4.dtsi diff | blob | history
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