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(parent: 8a9cebc) | patch
clk: at91: add PLLADIV driver
authorWenyou Yang <wenyou.yang@microchip.com>
Fri, 9 Feb 2018 03:34:51 +0000 (11:34 +0800)
committerTom Rini <trini@konsulko.com>
Fri, 16 Mar 2018 11:30:04 +0000 (07:30 -0400)
commite1692abb31084f9579eae88e02cfb149b4e57d11
treeefe417a3aa1f19076069eb4138e31ffa8731a66btree | snapshot
parent8a9cebc5f07b02f49b654466eb44bc7c0cd9ced2commit | diff
clk: at91: add PLLADIV driver

As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
drivers/clk/at91/Makefile diff | blob | history
drivers/clk/at91/clk-plladiv.c [new file with mode: 0644] blob
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