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(parent: 22ce8d0) | patch
drm/i915: Program DPLL P1 dividers consistently
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 15 Jul 2021 09:35:25 +0000 (12:35 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 25 Aug 2021 14:11:10 +0000 (17:11 +0300)
commite14b4b9dd6b0233136eb0a23aca48202f2d64086
tree7445ab7f3ff3add0c753f2118421cde9d59ba678tree | snapshot
parent22ce8d0e4b14a8400eca4f45650d838d2a8e71aacommit | diff
drm/i915: Program DPLL P1 dividers consistently

On g4x and pch the DPLL has two P1 dividers (for refresh rate
switching). Program the FPx1 P1 divider consistently to the reduced
clock P1 divider if available, otherwise just program it to the
same value as the FPx0 P1 divider.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_dpll.c diff | blob | history
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