]> git.baikalelectronics.ru Git - kernel.git/commit
rseq/selftests: Add support for RISC-V
authorVincent Chen <vincent.chen@sifive.com>
Tue, 8 Mar 2022 08:32:53 +0000 (16:32 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 22 Mar 2022 21:45:19 +0000 (14:45 -0700)
commite0fadd66bc119c34d5230272c7423df20c797801
tree35f6444e6bae8e031bcefcb457bd0de3ebbfe16a
parentc7599954dcf3ed40d071913e29a107c34e9c90ff
rseq/selftests: Add support for RISC-V

Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
tools/testing/selftests/rseq/param_test.c
tools/testing/selftests/rseq/rseq-riscv.h [new file with mode: 0644]
tools/testing/selftests/rseq/rseq.h